taxt.fit.eqn

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

--operation mode is normal

S31L3 = !S31L11;


--C1_stance[1] is speed:inst2|stance[1] at LC_X23_Y22_N2
--operation mode is arithmetic

C1_stance[1]_lut_out = C1L4;
C1_stance[1] = DFFEAS(C1_stance[1]_lut_out, GLOBAL(E1_clk_out), VCC, , , , , , );

--S31L1 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUT at LC_X23_Y22_N2
--operation mode is arithmetic

S31L1_cout_0 = C1_stance[1];
S31L1 = CARRY(S31L1_cout_0);

--S31L2 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUTCOUT1 at LC_X23_Y22_N2
--operation mode is arithmetic

S31L2_cout_1 = C1_stance[1];
S31L2 = CARRY(S31L2_cout_1);


--M2L73 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[46]~1041 at LC_X23_Y22_N0
--operation mode is normal

M2L73 = C1_stance[1] $ (S31L3);


--S31L4 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~46 at LC_X23_Y22_N6
--operation mode is arithmetic

S31L4 = S31L41 $ (!M2L13 & !M2L23);

--S31L5 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~48 at LC_X23_Y22_N6
--operation mode is arithmetic

S31L5_cout_0 = !M2L13 & !M2L23 & !S31L41;
S31L5 = CARRY(S31L5_cout_0);

--S31L6 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~48COUT1 at LC_X23_Y22_N6
--operation mode is arithmetic

S31L6_cout_1 = !M2L13 & !M2L23 & !S31L51;
S31L6 = CARRY(S31L6_cout_1);


--S21L3 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~41 at LC_X23_Y19_N9
--operation mode is normal

S21L3 = !S21L8;


--C1_stance[2] is speed:inst2|stance[2] at LC_X22_Y22_N7
--operation mode is arithmetic

C1_stance[2]_lut_out = C1L7;
C1_stance[2] = DFFEAS(C1_stance[2]_lut_out, GLOBAL(E1_clk_out), VCC, , , , , , );

--S21L1 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1]~COUT at LC_X22_Y22_N7
--operation mode is arithmetic

S21L1_cout_0 = C1_stance[2];
S21L1 = CARRY(S21L1_cout_0);

--S21L2 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1]~COUTCOUT1 at LC_X22_Y22_N7
--operation mode is arithmetic

S21L2_cout_1 = C1_stance[2];
S21L2 = CARRY(S21L2_cout_1);


--M2L83 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[47]~1042 at LC_X23_Y22_N1
--operation mode is normal

M2L83 = S31L3 & S31L4 # !S31L3 & (C1_stance[2] $ S21L3);


--S31L7 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~51 at LC_X23_Y22_N7
--operation mode is arithmetic

S31L7 = S31L5 $ (!M2L43 & !M2L33);

--S31L8 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~53 at LC_X23_Y22_N7
--operation mode is arithmetic

S31L8_cout_0 = !S31L5 & (M2L43 # M2L33);
S31L8 = CARRY(S31L8_cout_0);

--S31L9 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~53COUT1_70 at LC_X23_Y22_N7
--operation mode is arithmetic

S31L9_cout_1 = !S31L6 & (M2L43 # M2L33);
S31L9 = CARRY(S31L9_cout_1);


--S11L3 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~41 at LC_X22_Y19_N9
--operation mode is normal

S11L3 = !S11L5;


--C1_stance[3] is speed:inst2|stance[3] at LC_X25_Y18_N3
--operation mode is arithmetic

C1_stance[3]_lut_out = C1L01;
C1_stance[3] = DFFEAS(C1_stance[3]_lut_out, GLOBAL(E1_clk_out), VCC, , , , , , );

--S11L1 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]~COUT at LC_X25_Y18_N3
--operation mode is arithmetic

S11L1_cout_0 = C1_stance[3];
S11L1 = CARRY(S11L1_cout_0);

--S11L2 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]~COUTCOUT1 at LC_X25_Y18_N3
--operation mode is arithmetic

S11L2_cout_1 = C1_stance[3];
S11L2 = CARRY(S11L2_cout_1);


--M2L43 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[42]~1043 at LC_X22_Y19_N1
--operation mode is normal

M2L43 = !S21L3 & (C1_stance[3] $ S11L3);


--S21L4 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~46 at LC_X23_Y19_N6
--operation mode is arithmetic

S21L4 = S21L11 $ (!M2L62 & !M2L52);

--S21L5 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~48 at LC_X23_Y19_N6
--operation mode is arithmetic

S21L5_cout_0 = !M2L62 & !M2L52 & !S21L11;
S21L5 = CARRY(S21L5_cout_0);

--S21L6 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~48COUT1 at LC_X23_Y19_N6
--operation mode is arithmetic

S21L6_cout_1 = !M2L62 & !M2L52 & !S21L21;
S21L6 = CARRY(S21L6_cout_1);


--M2L33 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[42]~17 at LC_X22_Y22_N4
--operation mode is normal

M2L33 = S21L3 & (S21L4);


--M2L93 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[48]~1044 at LC_X23_Y22_N4
--operation mode is normal

M2L93 = S31L3 & S31L7 # !S31L3 & (M2L33 # M2L43);


--D1L23 is display:inst3|led7s4[6]~252 at LC_X24_Y23_N9
--operation mode is normal

D1L23 = M2L93 # M2L73 & (!M2L83 # !C1_stance[0]) # !M2L73 & (M2L83);


--D1L57 is display:inst3|led7s[6]~1743 at LC_X24_Y21_N0
--operation mode is normal

D1L57 = D1L47 & (!D1L23 # !D1_flg1[1]) # !D1L47 & D1_flg1[1] & (!D1L52);


--D1L67 is display:inst3|led7s[6]~1744 at LC_X22_Y23_N3
--operation mode is normal

D1L67 = D1L37 # D1L57 & !D1_flg1[2];


--D1L42 is display:inst3|led7s3[5]~134 at LC_X27_Y22_N7
--operation mode is normal

D1L42 = !Y2L5 & (Z5L5 & (Z6L1 # !Z4L5) # !Z5L5 & Z6L1 & !Z4L5);


--D1L71 is display:inst3|led7s2[5]~247 at LC_X23_Y23_N6
--operation mode is normal

D1L71 = !M5L12 & (M5L91 & (S62L1 # !M5L02) # !M5L91 & !M5L02 & S62L1);


--D1L01 is display:inst3|led7s1[5]~253 at LC_X26_Y18_N4
--operation mode is normal

D1L01 = !M6L93 & (M6L83 & M6L73 & C1_money[0] # !M6L83 & (M6L73 # C1_money[0]));


--D1L86 is display:inst3|led7s[5]~1745 at LC_X24_Y23_N0
--operation mode is normal

D1L86 = D1_flg1[0] & (D1_flg1[1] # D1L71) # !D1_flg1[0] & D1L01 & !D1_flg1[1];


--D1L13 is display:inst3|led7s4[5]~253 at LC_X24_Y23_N5
--operation mode is normal

D1L13 = !M2L93 & (C1_stance[0] & (M2L73 # !M2L83) # !C1_stance[0] & M2L73 & !M2L83);


--D1L96 is display:inst3|led7s[5]~1746 at LC_X24_Y23_N4
--operation mode is normal

D1L96 = D1_flg1[1] & (D1L86 & (D1L13) # !D1L86 & D1L42) # !D1_flg1[1] & D1L86;


--D1L04 is display:inst3|led7s6[5]~109 at LC_X22_Y23_N7
--operation mode is normal

D1L04 = !Y1L5 & (Z3L1 & (Z2L5 # !Z1L5) # !Z3L1 & !Z1L5 & Z2L5);


--D1L63 is display:inst3|led7s5[5]~132 at LC_X22_Y23_N9
--operation mode is normal

D1L63 = !M3L12 & (M3L02 & M3L91 & S6L1 # !M3L02 & (M3L91 # S6L1));


--D1L07 is display:inst3|led7s[5]~1747 at LC_X22_Y24_N8
--operation mode is normal

D1L07 = D1_flg1[0] & D1L04 # !D1_flg1[0] & (D1L63);


--D1L17 is display:inst3|led7s[5]~1748 at LC_X22_Y24_N2
--operation mode is normal

D1L17 = D1_flg1[2] & !D1_flg1[1] & (D1L07) # !D1_flg1[2] & (D1L96);


--D1L32 is display:inst3|led7s3[4]~135 at LC_X24_Y22_N7
--operation mode is normal

D1L32 = Z6L1 # Z4L5 & !Z5L5;


--D1L61 is display:inst3|led7s2[4]~248 at LC_X23_Y23_N0
--operation mode is normal

D1L61 = S62L1 # M5L02 & (!M5L91);


--D1L26 is display:inst3|led7s[4]~1749 at LC_X24_Y22_N9
--operation mode is normal

D1L26 = D1_flg1[0] & (D1_flg1[1] # D1L61) # !D1_flg1[0] & !D1_flg1[1] & D1L9;


--D1L36 is display:inst3|led7s[4]~1750 at LC_X24_Y22_N1
--operation mode is normal

D1L36 = D1L26 & (D1L03 # !D1_flg1[1]) # !D1L26 & D1_flg1[1] & D1L32;


--D1L46 is display:inst3|led7s[4]~1751 at LC_X21_Y23_N5
--operation mode is normal

D1L46 = Z3L1 # Z1L5 & !Z2L5;


--D1L56 is display:inst3|led7s[4]~1752 at LC_X21_Y23_N7
--operation mode is normal

D1L56 = M3L02 & (S91L5 & S91_add_sub_cella[1] # !S91L5 & (!S5L5));


--D1L66 is display:inst3|led7s[4]~1753 at LC_X21_Y23_N9
--operation mode is normal

D1L66 = D1_flg1[0] & (D1L46) # !D1_flg1[0] & (D1L56 # S6L1);


--D1L76 is display:inst3|led7s[4]~1754 at LC_X24_Y22_N3
--operation mode is normal

D1L76 = D1_flg1[2] & !D1_flg1[1] & D1L66 # !D1_flg1[2] & (D1L36);


--D1L22 is display:inst3|led7s3[3]~136 at LC_X27_Y22_N5
--operation mode is normal

D1L22 = !Y2L5 & (Z5L5 & Z6L1 & Z4L5 # !Z5L5 & (Z6L1 $ Z4L5));


--D1L51 is display:inst3|led7s2[3]~249 at LC_X23_Y23_N7
--operation mode is normal

D1L51 = !M5L12 & (M5L91 & M5L02 & S62L1 # !M5L91 & (M5L02 $ S62L1));


--D1L8 is display:inst3|led7s1[3]~254 at LC_X26_Y18_N0
--operation mode is normal

D1L8 = !M6L93 & (M6L83 & (M6L73 $ !C1_money[0]) # !M6L83 & !M6L73 & C1_money[0]);


--D1L85 is display:inst3|led7s[3]~1755 at LC_X24_Y23_N8
--operation mode is normal

D1L85 = D1_flg1[0] & (D1_flg1[1] # D1L51) # !D1_flg1[0] & D1L8 & !D1_flg1[1];


--D1L92 is display:inst3|led7s4[3]~254 at LC_X24_Y23_N6
--operation mode is normal

D1L92 = !M2L93 & (C1_stance[0] & (M2L73 $ !M2L83) # !C1_stance[0] & !M2L73 & M2L83);


--D1L95 is display:inst3|led7s[3]~1756 at LC_X24_Y23_N1
--operation mode is normal

D1L95 = D1_flg1[1] & (D1L85 & (D1L92) # !D1L85 & D1L22) # !D1_flg1[1] & D1L85;


--D1L93 is display:inst3|led7s6[3]~110 at LC_X22_Y23_N0
--operation mode is normal

D1L93 = !Y1L5 & (Z3L1 & (Z1L5 $ !Z2L5) # !Z3L1 & Z1L5 & !Z2L5);


--D1L53 is display:inst3|led7s5[3]~133 at LC_X22_Y23_N4
--operation mode is normal

D1L53 = !M3L12 & (M3L02 & (M3L91 $ !S6L1) # !M3L02 & !M3L91 & S6L1);


--D1L06 is display:inst3|led7s[3]~1757 at LC_X24_Y23_N2
--operation mode is normal

D1L06 = D1_flg1[0] & (D1L93) # !D1_flg1[0] & (D1L53);


--D1L16 is display:inst3|led7s[3]~1758 at LC_X24_Y23_N3
--operation mode is normal

D1L16 = D1_flg1[2] & (!D1_flg1[1] & D1L06) # !D1_flg1[2] & D1L95;