taxt.fit.eqn

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

S23L4_cout_1 = S52L5;
S23L4 = CARRY(S23L4_cout_1);


--M5L91 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[46]~591 at LC_X25_Y20_N5
--operation mode is normal

M5L91 = S23L5 & (!S23_add_sub_cella[1]) # !S23L5 & S52L5;


--S23L6 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~46 at LC_X25_Y20_N1
--operation mode is arithmetic

S23L6 = S23L61 $ (!M5L41 & !M5L31);

--S23L7 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~48 at LC_X25_Y20_N1
--operation mode is arithmetic

S23L7_cout_0 = !M5L41 & !M5L31 & !S23L61;
S23L7 = CARRY(S23L7_cout_0);

--S23L8 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~48COUT1 at LC_X25_Y20_N1
--operation mode is arithmetic

S23L8_cout_1 = !M5L41 & !M5L31 & !S23L71;
S23L8 = CARRY(S23L8_cout_1);


--S13L5 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~41 at LC_X27_Y20_N4
--operation mode is normal

S13L5 = !S13L01;


--S13_add_sub_cella[1] is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1] at LC_X27_Y20_N7
--operation mode is arithmetic

S13_add_sub_cella[1] = S42L5;

--S13L3 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1]~COUT at LC_X27_Y20_N7
--operation mode is arithmetic

S13L3_cout_0 = S42L5;
S13L3 = CARRY(S13L3_cout_0);

--S13L4 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1]~COUTCOUT1 at LC_X27_Y20_N7
--operation mode is arithmetic

S13L4_cout_1 = S42L5;
S13L4 = CARRY(S13L4_cout_1);


--M5L41 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[41]~18 at LC_X27_Y20_N5
--operation mode is normal

M5L41 = !S13_add_sub_cella[1] & (S13L5);


--S42L5 is d_to_b:inst1|lpm_divide:div_rtl_1|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~42 at LC_X26_Y20_N9
--operation mode is normal

S42L5 = !S42L7;


--M5L31 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[41]~13 at LC_X26_Y20_N0
--operation mode is normal

M5L31 = !S13L5 & S42L5;


--M5L02 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[47]~592 at LC_X25_Y20_N9
--operation mode is normal

M5L02 = S23L5 & S23L6 # !S23L5 & (M5L31 # M5L41);


--S23L9 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~51 at LC_X25_Y20_N2
--operation mode is arithmetic

S23L9 = S23L7 $ (!M5L51 & !M5L61);

--S23L01 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~53 at LC_X25_Y20_N2
--operation mode is arithmetic

S23L01_cout_0 = !S23L7 & (M5L51 # M5L61);
S23L01 = CARRY(S23L01_cout_0);

--S23L11 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~53COUT1_71 at LC_X25_Y20_N2
--operation mode is arithmetic

S23L11_cout_1 = !S23L8 & (M5L51 # M5L61);
S23L11 = CARRY(S23L11_cout_1);


--S32L5 is d_to_b:inst1|lpm_divide:div_rtl_1|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~42 at LC_X29_Y17_N9
--operation mode is normal

S32L5 = !S32L7;


--S03L5 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~41 at LC_X29_Y20_N4
--operation mode is normal

S03L5 = !S03L7;


--S03_add_sub_cella[1] is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1] at LC_X28_Y20_N6
--operation mode is arithmetic

S03_add_sub_cella[1] = S32L5;

--S03L3 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]~COUT at LC_X28_Y20_N6
--operation mode is arithmetic

S03L3_cout_0 = S32L5;
S03L3 = CARRY(S03L3_cout_0);

--S03L4 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]~COUTCOUT1 at LC_X28_Y20_N6
--operation mode is arithmetic

S03L4_cout_1 = S32L5;
S03L4 = CARRY(S03L4_cout_1);


--M5L61 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[42]~593 at LC_X28_Y20_N2
--operation mode is normal

M5L61 = !S13L5 & (S03L5 & !S03_add_sub_cella[1] # !S03L5 & (S32L5));


--S13L6 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~46 at LC_X27_Y20_N1
--operation mode is arithmetic

S13L6 = S13L31 $ (!M5L7 & !M5L8);

--S13L7 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~48 at LC_X27_Y20_N1
--operation mode is arithmetic

S13L7_cout_0 = !M5L7 & !M5L8 & !S13L31;
S13L7 = CARRY(S13L7_cout_0);

--S13L8 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~48COUT1 at LC_X27_Y20_N1
--operation mode is arithmetic

S13L8_cout_1 = !M5L7 & !M5L8 & !S13L41;
S13L8 = CARRY(S13L8_cout_1);


--M5L51 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[42]~17 at LC_X27_Y20_N6
--operation mode is normal

M5L51 = S13L6 & (S13L5);


--M5L12 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[48]~594 at LC_X25_Y20_N8
--operation mode is normal

M5L12 = S23L5 & (S23L9) # !S23L5 & (M5L61 # M5L51);


--D1L81 is display:inst3|led7s2[6]~246 at LC_X24_Y21_N9
--operation mode is normal

D1L81 = M5L12 # M5L02 & (!M5L91 # !S62L1) # !M5L02 & (M5L91);


--C1_money[0] is speed:inst2|money[0] at LC_X26_Y18_N9
--operation mode is normal

C1_money[0]_lut_out = C1_time[0] # !C1L002;
C1_money[0] = DFFEAS(C1_money[0]_lut_out, GLOBAL(E1_clk_out), VCC, , , , , , );


--S83L5 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~41 at LC_X26_Y17_N9
--operation mode is normal

S83L5 = !S83L31;


--S83_add_sub_cella[1] is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1] at LC_X26_Y17_N2
--operation mode is arithmetic

S83_add_sub_cella[1] = C1_money[1];

--S83L3 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUT at LC_X26_Y17_N2
--operation mode is arithmetic

S83L3_cout_0 = S83_add_sub_cella[1];
S83L3 = CARRY(S83L3_cout_0);

--S83L4 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUTCOUT1 at LC_X26_Y17_N2
--operation mode is arithmetic

S83L4_cout_1 = S83_add_sub_cella[1];
S83L4 = CARRY(S83L4_cout_1);


--M6L73 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[46]~1041 at LC_X26_Y18_N5
--operation mode is normal

M6L73 = S83L5 $ (S83_add_sub_cella[1]);


--S83L6 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~46 at LC_X26_Y17_N6
--operation mode is arithmetic

S83L6 = S83L61 $ (!M6L13 & !M6L23);

--S83L7 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~48 at LC_X26_Y17_N6
--operation mode is arithmetic

S83L7_cout_0 = !M6L13 & !M6L23 & !S83L61;
S83L7 = CARRY(S83L7_cout_0);

--S83L8 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~48COUT1 at LC_X26_Y17_N6
--operation mode is arithmetic

S83L8_cout_1 = !M6L13 & !M6L23 & !S83L71;
S83L8 = CARRY(S83L8_cout_1);


--S73L5 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~41 at LC_X27_Y16_N4
--operation mode is normal

S73L5 = !S73L01;


--S73_add_sub_cella[1] is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1] at LC_X27_Y16_N6
--operation mode is arithmetic

S73_add_sub_cella[1] = C1_money[2];

--S73L3 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1]~COUT at LC_X27_Y16_N6
--operation mode is arithmetic

S73L3_cout_0 = S73_add_sub_cella[1];
S73L3 = CARRY(S73L3_cout_0);

--S73L4 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1]~COUTCOUT1 at LC_X27_Y16_N6
--operation mode is arithmetic

S73L4_cout_1 = S73_add_sub_cella[1];
S73L4 = CARRY(S73L4_cout_1);


--M6L83 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[47]~1042 at LC_X26_Y18_N6
--operation mode is normal

M6L83 = S83L5 & S83L6 # !S83L5 & (S73L5 $ S73_add_sub_cella[1]);


--S83L9 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~51 at LC_X26_Y17_N7
--operation mode is arithmetic

S83L9 = S83L7 $ (!M6L33 & !M6L43);

--S83L01 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~53 at LC_X26_Y17_N7
--operation mode is arithmetic

S83L01_cout_0 = !S83L7 & (M6L33 # M6L43);
S83L01 = CARRY(S83L01_cout_0);

--S83L11 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~53COUT1_72 at LC_X26_Y17_N7
--operation mode is arithmetic

S83L11_cout_1 = !S83L8 & (M6L33 # M6L43);
S83L11 = CARRY(S83L11_cout_1);


--S63L5 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~41 at LC_X28_Y17_N9
--operation mode is normal

S63L5 = !S63L7;


--S63_add_sub_cella[1] is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1] at LC_X28_Y17_N2
--operation mode is arithmetic

S63_add_sub_cella[1] = C1_money[3];

--S63L3 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]~COUT at LC_X28_Y17_N2
--operation mode is arithmetic

S63L3_cout_0 = S63_add_sub_cella[1];
S63L3 = CARRY(S63L3_cout_0);

--S63L4 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]~COUTCOUT1 at LC_X28_Y17_N2
--operation mode is arithmetic

S63L4_cout_1 = S63_add_sub_cella[1];
S63L4 = CARRY(S63L4_cout_1);


--M6L43 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[42]~1043 at LC_X27_Y17_N6
--operation mode is normal

M6L43 = !S73L5 & (S63_add_sub_cella[1] $ S63L5);


--S73L6 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~46 at LC_X27_Y16_N1
--operation mode is arithmetic

S73L6 = S73L31 $ (!M6L52 & !M6L62);

--S73L7 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~48 at LC_X27_Y16_N1
--operation mode is arithmetic

S73L7_cout_0 = !M6L52 & !M6L62 & !S73L31;
S73L7 = CARRY(S73L7_cout_0);

--S73L8 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~48COUT1 at LC_X27_Y16_N1
--operation mode is arithmetic

S73L8_cout_1 = !M6L52 & !M6L62 & !S73L41;
S73L8 = CARRY(S73L8_cout_1);


--M6L33 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[42]~17 at LC_X27_Y18_N4
--operation mode is normal

M6L33 = S73L5 & S73L6;


--M6L93 is d_to_b:inst1|lpm_divide:mod_rtl_3|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[48]~1044 at LC_X26_Y17_N1
--operation mode is normal

M6L93 = S83L5 & S83L9 # !S83L5 & (M6L33 # M6L43);


--D1L11 is display:inst3|led7s1[6]~252 at LC_X26_Y18_N7
--operation mode is normal

D1L11 = M6L93 # M6L83 & (!C1_money[0] # !M6L73) # !M6L83 & M6L73;


--D1L47 is display:inst3|led7s[6]~1742 at LC_X24_Y21_N7
--operation mode is normal

D1L47 = D1_flg1[1] & (D1_flg1[0]) # !D1_flg1[1] & (D1_flg1[0] & !D1L81 # !D1_flg1[0] & (!D1L11));


--S31L3 is d_to_b:inst|lpm_divide:mod_rtl_4|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~41 at LC_X23_Y22_N9