taxt.fit.eqn

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

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--D1_flg1[2] is display:inst3|flg1[2] at LC_X22_Y24_N3
--operation mode is normal

D1_flg1[2]_lut_out = D1_flg1[0] & D1_flg1[1] & (!D1_flg1[2]) # !D1_flg1[0] & (D1_flg1[2]);
D1_flg1[2] = DFFEAS(D1_flg1[2]_lut_out, GLOBAL(F1_clk_out), VCC, , , , , , );


--D1_flg1[1] is display:inst3|flg1[1] at LC_X22_Y24_N6
--operation mode is normal

D1_flg1[1]_lut_out = D1_flg1[1] & !D1_flg1[0] # !D1_flg1[1] & D1_flg1[0] & (!D1_flg1[2]);
D1_flg1[1] = DFFEAS(D1_flg1[1]_lut_out, GLOBAL(F1_clk_out), VCC, , , , , , );


--D1L27 is display:inst3|led7s[6]~1740 at LC_X22_Y24_N1
--operation mode is normal

D1L27 = !D1_flg1[1] & (D1_flg1[2]);


--D1_flg1[0] is display:inst3|flg1[0] at LC_X22_Y24_N5
--operation mode is normal

D1_flg1[0]_lut_out = !D1_flg1[0];
D1_flg1[0] = DFFEAS(D1_flg1[0]_lut_out, GLOBAL(F1_clk_out), VCC, , , , , , );


--S6L1 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~44 at LC_X21_Y22_N9
--operation mode is normal

S6L1 = !S6L3;


--S5L5 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~42 at LC_X18_Y23_N4
--operation mode is normal

S5L5 = !S5L7;


--S91L5 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~41 at LC_X17_Y23_N4
--operation mode is normal

S91L5 = !S91L31;


--S91_add_sub_cella[1] is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1] at LC_X18_Y23_N6
--operation mode is arithmetic

S91_add_sub_cella[1] = S5L5;

--S91L3 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUT at LC_X18_Y23_N6
--operation mode is arithmetic

S91L3_cout_0 = S5L5;
S91L3 = CARRY(S91L3_cout_0);

--S91L4 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUTCOUT1 at LC_X18_Y23_N6
--operation mode is arithmetic

S91L4_cout_1 = S5L5;
S91L4 = CARRY(S91L4_cout_1);


--M3L91 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[46]~591 at LC_X22_Y23_N2
--operation mode is normal

M3L91 = S91L5 & (!S91_add_sub_cella[1]) # !S91L5 & S5L5;


--S91L6 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~46 at LC_X17_Y23_N1
--operation mode is arithmetic

S91L6 = S91L61 $ (!M3L31 & !M3L41);

--S91L7 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~48 at LC_X17_Y23_N1
--operation mode is arithmetic

S91L7_cout_0 = !M3L31 & !M3L41 & !S91L61;
S91L7 = CARRY(S91L7_cout_0);

--S91L8 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~48COUT1 at LC_X17_Y23_N1
--operation mode is arithmetic

S91L8_cout_1 = !M3L31 & !M3L41 & !S91L71;
S91L8 = CARRY(S91L8_cout_1);


--S81L5 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~41 at LC_X17_Y22_N9
--operation mode is normal

S81L5 = !S81L01;


--S81_add_sub_cella[1] is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1] at LC_X18_Y21_N1
--operation mode is arithmetic

S81_add_sub_cella[1] = S4L5;

--S81L3 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1]~COUT at LC_X18_Y21_N1
--operation mode is arithmetic

S81L3_cout_0 = S4L5;
S81L3 = CARRY(S81L3_cout_0);

--S81L4 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[1]~COUTCOUT1 at LC_X18_Y21_N1
--operation mode is arithmetic

S81L4_cout_1 = S4L5;
S81L4 = CARRY(S81L4_cout_1);


--M3L41 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[41]~18 at LC_X17_Y23_N8
--operation mode is normal

M3L41 = S81L5 & (!S81_add_sub_cella[1]);


--S4L5 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~42 at LC_X18_Y22_N4
--operation mode is normal

S4L5 = !S4L7;


--M3L31 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[41]~13 at LC_X17_Y23_N6
--operation mode is normal

M3L31 = S4L5 & !S81L5;


--M3L02 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[47]~592 at LC_X17_Y23_N7
--operation mode is normal

M3L02 = S91L5 & S91L6 # !S91L5 & (M3L41 # M3L31);


--S91L9 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~51 at LC_X17_Y23_N2
--operation mode is arithmetic

S91L9 = S91L7 $ (!M3L51 & !M3L61);

--S91L01 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~53 at LC_X17_Y23_N2
--operation mode is arithmetic

S91L01_cout_0 = !S91L7 & (M3L51 # M3L61);
S91L01 = CARRY(S91L01_cout_0);

--S91L11 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~53COUT1_71 at LC_X17_Y23_N2
--operation mode is arithmetic

S91L11_cout_1 = !S91L8 & (M3L51 # M3L61);
S91L11 = CARRY(S91L11_cout_1);


--S3L5 is d_to_b:inst|lpm_divide:div_rtl_5|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~42 at LC_X18_Y19_N9
--operation mode is normal

S3L5 = !S3L7;


--S71L5 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~41 at LC_X17_Y21_N9
--operation mode is normal

S71L5 = !S71L7;


--S71_add_sub_cella[1] is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1] at LC_X17_Y22_N3
--operation mode is arithmetic

S71_add_sub_cella[1] = S3L5;

--S71L3 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]~COUT at LC_X17_Y22_N3
--operation mode is arithmetic

S71L3_cout_0 = S3L5;
S71L3 = CARRY(S71L3_cout_0);

--S71L4 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_7|add_sub_cella[1]~COUTCOUT1 at LC_X17_Y22_N3
--operation mode is arithmetic

S71L4_cout_1 = S3L5;
S71L4 = CARRY(S71L4_cout_1);


--M3L61 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[42]~593 at LC_X17_Y22_N0
--operation mode is normal

M3L61 = !S81L5 & (S71L5 & !S71_add_sub_cella[1] # !S71L5 & (S3L5));


--S81L6 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~46 at LC_X17_Y22_N6
--operation mode is arithmetic

S81L6 = S81L31 $ (!M3L7 & !M3L8);

--S81L7 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~48 at LC_X17_Y22_N6
--operation mode is arithmetic

S81L7_cout_0 = !M3L7 & !M3L8 & !S81L31;
S81L7 = CARRY(S81L7_cout_0);

--S81L8 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~48COUT1 at LC_X17_Y22_N6
--operation mode is arithmetic

S81L8_cout_1 = !M3L7 & !M3L8 & !S81L41;
S81L8 = CARRY(S81L8_cout_1);


--M3L51 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[42]~17 at LC_X18_Y24_N2
--operation mode is normal

M3L51 = S81L5 & (S81L6);


--M3L12 is d_to_b:inst|lpm_divide:mod_rtl_6|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|StageOut[48]~594 at LC_X22_Y23_N8
--operation mode is normal

M3L12 = S91L5 & (S91L9) # !S91L5 & (M3L61 # M3L51);


--D1L73 is display:inst3|led7s5[6]~131 at LC_X22_Y23_N1
--operation mode is normal

D1L73 = M3L12 # M3L02 & (!S6L1 # !M3L91) # !M3L02 & M3L91;


--Z3L1 is d_to_b:inst|lpm_divide:div_rtl_7|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_9|add_sub_cella[3]~64 at LC_X23_Y21_N7
--operation mode is normal

Z3L1_carry_eqn = (!Z3L9 & Z3L3) # (Z3L9 & Z3L4);
Z3L1 = !Z3L1_carry_eqn;


--Z2L5 is d_to_b:inst|lpm_divide:div_rtl_7|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_8|add_sub_cella[3]~61 at LC_X23_Y20_N7
--operation mode is normal

Z2L5_carry_eqn = (!Z2L31 & Z2L7) # (Z2L31 & Z2L8);
Z2L5 = !Z2L5_carry_eqn;


--Z1L5 is d_to_b:inst|lpm_divide:div_rtl_7|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_7|add_sub_cella[3]~61 at LC_X21_Y21_N7
--operation mode is normal

Z1L5_carry_eqn = (!Z1L01 & Z1L7) # (Z1L01 & Z1L8);
Z1L5 = !Z1L5_carry_eqn;


--Y1L5 is d_to_b:inst|lpm_divide:div_rtl_7|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_qe8:add_sub_6|add_sub_cella[3]~52 at LC_X22_Y20_N6
--operation mode is normal

Y1L5_carry_eqn = (!Y1L31 & Y1L7) # (Y1L31 & Y1L8);
Y1L5 = Y1L5_carry_eqn;


--D1L14 is display:inst3|led7s6[6]~108 at LC_X22_Y23_N6
--operation mode is normal

D1L14 = Y1L5 # Z1L5 & (!Z2L5 # !Z3L1) # !Z1L5 & (Z2L5);


--D1L37 is display:inst3|led7s[6]~1741 at LC_X22_Y23_N5
--operation mode is normal

D1L37 = D1L27 & (D1_flg1[0] & !D1L14 # !D1_flg1[0] & (!D1L73));


--Z6L1 is d_to_b:inst1|lpm_divide:div_rtl_0|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_9|add_sub_cella[3]~68 at LC_X25_Y22_N7
--operation mode is normal

Z6L1_carry_eqn = (!Z6L9 & Z6L3) # (Z6L9 & Z6L4);
Z6L1 = !Z6L1_carry_eqn;


--Z5L5 is d_to_b:inst1|lpm_divide:div_rtl_0|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_8|add_sub_cella[3]~61 at LC_X26_Y22_N7
--operation mode is normal

Z5L5_carry_eqn = (!Z5L31 & Z5L7) # (Z5L31 & Z5L8);
Z5L5 = !Z5L5_carry_eqn;


--Z4L5 is d_to_b:inst1|lpm_divide:div_rtl_0|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_re8:add_sub_7|add_sub_cella[3]~61 at LC_X29_Y22_N7
--operation mode is normal

Z4L5_carry_eqn = (!Z4L01 & Z4L7) # (Z4L01 & Z4L8);
Z4L5 = !Z4L5_carry_eqn;


--Y2L5 is d_to_b:inst1|lpm_divide:div_rtl_0|lpm_divide_0nf:auto_generated|sign_div_unsign_2jg:divider|alt_u_div_9od:divider|add_sub_qe8:add_sub_6|add_sub_cella[3]~52 at LC_X28_Y21_N6
--operation mode is normal

Y2L5_carry_eqn = (!Y2L31 & Y2L7) # (Y2L31 & Y2L8);
Y2L5 = Y2L5_carry_eqn;


--D1L52 is display:inst3|led7s3[6]~133 at LC_X24_Y21_N5
--operation mode is normal

D1L52 = Y2L5 # Z4L5 & (!Z5L5 # !Z6L1) # !Z4L5 & (Z5L5);


--S62L1 is d_to_b:inst1|lpm_divide:div_rtl_1|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~48 at LC_X25_Y21_N4
--operation mode is normal

S62L1 = !S62L3;


--S52L5 is d_to_b:inst1|lpm_divide:div_rtl_1|lpm_divide_tmf:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_8|add_sub_cella[2]~42 at LC_X26_Y19_N9
--operation mode is normal

S52L5 = !S52L7;


--S23L5 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[2]~41 at LC_X25_Y20_N4
--operation mode is normal

S23L5 = !S23L31;


--S23_add_sub_cella[1] is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1] at LC_X25_Y20_N6
--operation mode is arithmetic

S23_add_sub_cella[1] = S52L5;

--S23L3 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUT at LC_X25_Y20_N6
--operation mode is arithmetic

S23L3_cout_0 = S52L5;
S23L3 = CARRY(S23L3_cout_0);

--S23L4 is d_to_b:inst1|lpm_divide:mod_rtl_2|lpm_divide_0ff:auto_generated|sign_div_unsign_vig:divider|alt_u_div_3od:divider|add_sub_oe8:add_sub_9|add_sub_cella[1]~COUTCOUT1 at LC_X25_Y20_N6
--operation mode is arithmetic