d_to_b.vhd

FPGA VHDL 语言的的士计费系统！与现有的的士计费系统功能一样。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY d_to_b is
port(ax:in integer range 999 downto 0;
     q3:out integer range 9 downto 0;
     q2:out integer range 9 downto 0;
     q1:out integer range 9 downto 0);
end;
architecture one of d_to_b is
begin
q1<=ax mod 10;
q2<=(ax/10) mod 10;
q3<=ax/100;
end;