addr_decode.v

来自「8位RISC CPU,包括alu,count,machine等等」· Verilog 代码 · 共 14 行

module addr_decode(addr,rom_sel,ram_sel);
  output rom_sel,ram_sel;
  input [12:0]addr;
  reg rom_sel,ram_sel;
always@(addr)
begin
  casex(addr)
   13'b11xxxxxxxxxxx:{rom_sel,ram_sel}<=2'b01;
   13'b0xxxxxxxxxxxx:{rom_sel,ram_sel}<=2'b10;
   13'b10xxxxxxxxxxx:{rom_sel,ram_sel}<=2'b10;
   default:{rom_sel,ram_sel}<=2'b00;
  endcase
 end
endmodule