accum.v

来自「8位RISC CPU,包括alu,count,machine等等」· Verilog 代码 · 共 14 行

module accum(accum,data,ena,clk1,rst);
output[7:0]accum;
input [7:0]data;
input ena,clk1,rst;
reg[7:0] accum;
always@(posedge clk1)
  begin
    if(rst)
      accum<=8'b00000000;
    else
      if(ena)
       accum<=data;
  end
endmodule