sr testbench.txt

Shift Register. VHDL code and its testbench.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY shifter_tb_vhd IS

END shifter_tb_vhd;

 

ARCHITECTURE behavior OF shifter_tb_vhd IS

 

            -- Component Declaration for the Unit Under Test (UUT)

            COMPONENT shift_reg

            PORT(

                        I : IN std_logic;

                        clock : IN std_logic;

                        shift : IN std_logic;         

                        Q : OUT std_logic_vector

                        );

            END COMPONENT;

 

            --Inputs

            SIGNAL I :  std_logic := '0';

            SIGNAL clock :  std_logic := '0';

            SIGNAL shift :  std_logic := '0';

 

            --Outputs

            SIGNAL Q :  std_logic_vector(2 downto 0);

 

BEGIN

 

            -- Instantiate the Unit Under Test (UUT)

            uut: shift_reg PORT MAP(

                        I => I,

                        clock => clock,

                        shift => shift,

                        Q => Q

            );

 

            clk_p: PROCESS

                        begin

                        CLOCK <= '0';

                        wait FOR 10 ns;

                        clock <= '1';

                        wait for 10 ns;

            END PROCESS;

 

            tb : PROCESS

            BEGIN

 

                        -- Wait 100 ns for global reset to finish

                        wait for 100 ns;

                        I<=  '1';

                        shift <= '1';                  -- Place stimulus here

                        wait for 100 ns;

                        I<= '0';

                        wait for 100 ns;

                        I<= '1';

 

                        wait; -- will wait forever

            END PROCESS;

 

END;