encoder.tan.qmsg

来自「编码器信号处理 经过倍频器进行四倍频 后 同时完成鉴相 计数」· QMSG 代码 · 共 13 行 · 第 1/3 页

{ "Info" "ITDB_TH_RESULT" "sta\[1\] QA clk -3.000 ns register " "Info: th for register \"sta\[1\]\" (data pin = \"QA\", clock pin = \"clk\") is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 38 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 38; CLK Node = 'clk'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns sta\[1\] 2 REG LC70 167 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC70; Fanout = 167; REG Node = 'sta\[1\]'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { clk sta[1] } "NODE_NAME" } } { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk sta[1] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out sta[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns QA 1 PIN PIN_81 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 1; PIN Node = 'QA'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { QA } "NODE_NAME" } } { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns sta\[1\] 2 REG LC70 167 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC70; Fanout = 167; REG Node = 'sta\[1\]'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { QA sta[1] } "NODE_NAME" } } { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { QA sta[1] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { QA QA~out sta[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk sta[1] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out sta[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { QA sta[1] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { QA QA~out sta[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "97 " "Info: Allocated 97 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 29 22:30:20 2009 " "Info: Processing ended: Sun Mar 29 22:30:20 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}