encoder.tan.qmsg

来自「编码器信号处理 经过倍频器进行四倍频 后 同时完成鉴相 计数」· QMSG 代码 · 共 13 行 · 第 1/3 页

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 6 -1 0 } } { "e:/install/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/install/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:db_rtl_0\|p8count:p8c\[0\]\|8 register lpm_counter:db_rtl_0\|p8count:p8c\[0\]\|2 43.48 MHz 23.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 43.48 MHz between source register \"lpm_counter:db_rtl_0\|p8count:p8c\[0\]\|8\" and destination register \"lpm_counter:db_rtl_0\|p8count:p8c\[0\]\|2\" (period= 23.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "18.000 ns + Longest register register " "Info: + Longest register to register delay is 18.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:db_rtl_0\|p8count:p8c\[0\]\|8 1 REG LC66 105 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC66; Fanout = 105; REG Node = 'lpm_counter:db_rtl_0\|p8count:p8c\[0\]\|8'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:db_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "p8count.bdf" "" { Schematic "e:/install/altera/70/quartus/libraries/others/maxplus2/p8count.bdf" { { 112 960 1024 192 "8" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns lpm_add_sub:Add1\|addcore:adder\[0\]\|a_csnbuffer:result_node\|sout_node\[6\]~26 2 COMB LC9 8 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC9; Fanout = 8; COMB Node = 'lpm_add_sub:Add1\|addcore:adder\[0\]\|a_csnbuffer:result_node\|sout_node\[6\]~26'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.000 ns" { lpm_counter:db_rtl_0|p8count:p8c[0]|8 lpm_add_sub:Add1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~26 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/install/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf" 42 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 17.000 ns lpm_counter:db_rtl_0\|p8count:p8c\[0\]\|31~94 3 COMB LC53 1 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 17.000 ns; Loc. = LC53; Fanout = 1; COMB Node = 'lpm_counter:db_rtl_0\|p8count:p8c\[0\]\|31~94'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { lpm_add_sub:Add1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~26 lpm_counter:db_rtl_0|p8count:p8c[0]|31~94 } "NODE_NAME" } } { "p8count.bdf" "" { Schematic "e:/install/altera/70/quartus/libraries/others/maxplus2/p8count.bdf" { { 1288 768 832 1328 "31" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 18.000 ns lpm_counter:db_rtl_0\|p8count:p8c\[0\]\|2 4 REG LC54 69 " "Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 18.000 ns; Loc. = LC54; Fanout = 69; REG Node = 'lpm_counter:db_rtl_0\|p8count:p8c\[0\]\|2'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { lpm_counter:db_rtl_0|p8count:p8c[0]|31~94 lpm_counter:db_rtl_0|p8count:p8c[0]|2 } "NODE_NAME" } } { "p8count.bdf" "" { Schematic "e:/install/altera/70/quartus/libraries/others/maxplus2/p8count.bdf" { { 1288 960 1024 1368 "2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns ( 77.78 % ) " "Info: Total cell delay = 14.000 ns ( 77.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 22.22 % ) " "Info: Total interconnect delay = 4.000 ns ( 22.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "18.000 ns" { lpm_counter:db_rtl_0|p8count:p8c[0]|8 lpm_add_sub:Add1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~26 lpm_counter:db_rtl_0|p8count:p8c[0]|31~94 lpm_counter:db_rtl_0|p8count:p8c[0]|2 } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "18.000 ns" { lpm_counter:db_rtl_0|p8count:p8c[0]|8 lpm_add_sub:Add1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~26 lpm_counter:db_rtl_0|p8count:p8c[0]|31~94 lpm_counter:db_rtl_0|p8count:p8c[0]|2 } { 0.000ns 2.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 6.000ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 38 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 38; CLK Node = 'clk'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns lpm_counter:db_rtl_0\|p8count:p8c\[0\]\|2 2 REG LC54 69 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC54; Fanout = 69; REG Node = 'lpm_counter:db_rtl_0\|p8count:p8c\[0\]\|2'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { clk lpm_counter:db_rtl_0|p8count:p8c[0]|2 } "NODE_NAME" } } { "p8count.bdf" "" { Schematic "e:/install/altera/70/quartus/libraries/others/maxplus2/p8count.bdf" { { 1288 960 1024 1368 "2" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk lpm_counter:db_rtl_0|p8count:p8c[0]|2 } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:db_rtl_0|p8count:p8c[0]|2 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 38 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 38; CLK Node = 'clk'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns lpm_counter:db_rtl_0\|p8count:p8c\[0\]\|8 2 REG LC66 105 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC66; Fanout = 105; REG Node = 'lpm_counter:db_rtl_0\|p8count:p8c\[0\]\|8'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { clk lpm_counter:db_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "p8count.bdf" "" { Schematic "e:/install/altera/70/quartus/libraries/others/maxplus2/p8count.bdf" { { 112 960 1024 192 "8" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk lpm_counter:db_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:db_rtl_0|p8count:p8c[0]|8 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk lpm_counter:db_rtl_0|p8count:p8c[0]|2 } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:db_rtl_0|p8count:p8c[0]|2 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk lpm_counter:db_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:db_rtl_0|p8count:p8c[0]|8 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "p8count.bdf" "" { Schematic "e:/install/altera/70/quartus/libraries/others/maxplus2/p8count.bdf" { { 112 960 1024 192 "8" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "p8count.bdf" "" { Schematic "e:/install/altera/70/quartus/libraries/others/maxplus2/p8count.bdf" { { 1288 960 1024 1368 "2" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "18.000 ns" { lpm_counter:db_rtl_0|p8count:p8c[0]|8 lpm_add_sub:Add1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~26 lpm_counter:db_rtl_0|p8count:p8c[0]|31~94 lpm_counter:db_rtl_0|p8count:p8c[0]|2 } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "18.000 ns" { lpm_counter:db_rtl_0|p8count:p8c[0]|8 lpm_add_sub:Add1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[6]~26 lpm_counter:db_rtl_0|p8count:p8c[0]|31~94 lpm_counter:db_rtl_0|p8count:p8c[0]|2 } { 0.000ns 2.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 6.000ns 1.000ns } "" } } { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk lpm_counter:db_rtl_0|p8count:p8c[0]|2 } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:db_rtl_0|p8count:p8c[0]|2 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk lpm_counter:db_rtl_0|p8count:p8c[0]|8 } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out lpm_counter:db_rtl_0|p8count:p8c[0]|8 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "sta\[1\] QA clk 11.000 ns register " "Info: tsu for register \"sta\[1\]\" (data pin = \"QA\", clock pin = \"clk\") is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns QA 1 PIN PIN_81 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 1; PIN Node = 'QA'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { QA } "NODE_NAME" } } { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns sta\[1\] 2 REG LC70 167 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC70; Fanout = 167; REG Node = 'sta\[1\]'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.000 ns" { QA sta[1] } "NODE_NAME" } } { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { QA sta[1] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { QA QA~out sta[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 38 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 38; CLK Node = 'clk'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns sta\[1\] 2 REG LC70 167 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC70; Fanout = 167; REG Node = 'sta\[1\]'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { clk sta[1] } "NODE_NAME" } } { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk sta[1] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out sta[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { QA sta[1] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { QA QA~out sta[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } "" } } { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk sta[1] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out sta[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk y\[15\] y\[0\]~en 15.000 ns register " "Info: tco from clock \"clk\" to destination pin \"y\[15\]\" through register \"y\[0\]~en\" is 15.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 38 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 38; CLK Node = 'clk'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns y\[0\]~en 2 REG LC80 16 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC80; Fanout = 16; REG Node = 'y\[0\]~en'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.000 ns" { clk y[0]~en } "NODE_NAME" } } { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk y[0]~en } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out y[0]~en } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 44 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.000 ns + Longest register pin " "Info: + Longest register to pin delay is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns y\[0\]~en 1 REG LC80 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC80; Fanout = 16; REG Node = 'y\[0\]~en'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { y[0]~en } "NODE_NAME" } } { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(9.000 ns) 11.000 ns y\[15\] 2 PIN PIN_9 0 " "Info: 2: + IC(2.000 ns) + CELL(9.000 ns) = 11.000 ns; Loc. = PIN_9; Fanout = 0; PIN Node = 'y\[15\]'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.000 ns" { y[0]~en y[15] } "NODE_NAME" } } { "encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns ( 81.82 % ) " "Info: Total cell delay = 9.000 ns ( 81.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 18.18 % ) " "Info: Total interconnect delay = 2.000 ns ( 18.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.000 ns" { y[0]~en y[15] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "11.000 ns" { y[0]~en y[15] } { 0.000ns 2.000ns } { 0.000ns 9.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { clk y[0]~en } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out y[0]~en } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } "" } } { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "11.000 ns" { y[0]~en y[15] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "11.000 ns" { y[0]~en y[15] } { 0.000ns 2.000ns } { 0.000ns 9.000ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}