encoder.vhd

编码器信号处理 经过倍频器进行四倍频 后 同时完成鉴相 计数

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity encoder is
   port(      clk,QA,QB,sel:in std_logic;                        
              dir:out std_logic;
              y:out std_logic_vector(15 downto 0));
end encoder;

architecture rtl of encoder is
signal sta:std_logic_vector(1 downto 0);
signal db:std_logic_vector(15 downto 0);
signal presta:std_logic_vector(1 downto 0);
begin
process(QA,QB,clk,sel,db)
    begin
     if clk'event and clk='1' then
            presta<=sta;
            sta(1)<=QA;sta(0)<=QB;
                       
       if(presta="00" and sta="10") then
           db<=db+"01";   dir<='0';     
       elsif(presta="10" and sta="11") then
           db<=db+"01";   dir<='0';
       elsif(presta="11" and sta="01") then
           db<=db+"01";   dir<='0';
       elsif(presta="01" and sta="00") then
           db<=db+"01";   dir<='0';
       elsif(presta="00" and sta="01") then
           db<=db-"01";   dir<='1';
       elsif(presta="01" and sta="11") then
          db<=db-"01";    dir<='1';
       elsif(presta="11" and sta="10") then
           db<=db-"01";   dir<='1';
       elsif(presta="10" and sta="00") then
           db<=db-"01";      dir<='1';     
       else db<=db;           
      end if;
    end if;
end process;
process(sel,clk,db)--output 
	begin 
	  if (clk'event and clk='1') then        
	       if  sel='0' then
	        y<=db ;
	      else
	      y<="ZZZZZZZZZZZZZZZZ";  
	      end if;
     end if;
end process ;
end rtl;