encoder.rpt

编码器信号处理 经过倍频器进行四倍频 后 同时完成鉴相 计数

Project Information                                    f:\encoder3\encoder.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/28/2009 22:55:06

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was unsuccessful


ENCODER


** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

encoder   EPM7128SLC84-15  4        17       0      161     137         No Fit

User Pins:                 4        17       0  



Project Information                                    f:\encoder3\encoder.rpt

** PROJECT COMPILATION MESSAGES **

Error: Project does not fit in specified device(s)
Error: No fit found, generating Report File

(See individual chip error summaries for additional information)

Project Information                                    f:\encoder3\encoder.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'clk' chosen for auto global Clock


Project Information                                    f:\encoder3\encoder.rpt

** FILE HIERARCHY **



|lpm_add_sub:421|
|lpm_add_sub:421|addcore:adder|
|lpm_add_sub:421|addcore:adder|addcore:adder1|
|lpm_add_sub:421|addcore:adder|addcore:adder0|
|lpm_add_sub:421|altshift:result_ext_latency_ffs|
|lpm_add_sub:421|altshift:carry_ext_latency_ffs|
|lpm_add_sub:421|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:504|
|lpm_add_sub:504|addcore:adder|
|lpm_add_sub:504|addcore:adder|addcore:adder1|
|lpm_add_sub:504|addcore:adder|addcore:adder0|
|lpm_add_sub:504|altshift:result_ext_latency_ffs|
|lpm_add_sub:504|altshift:carry_ext_latency_ffs|
|lpm_add_sub:504|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:587|
|lpm_add_sub:587|addcore:adder|
|lpm_add_sub:587|addcore:adder|addcore:adder1|
|lpm_add_sub:587|addcore:adder|addcore:adder0|
|lpm_add_sub:587|altshift:result_ext_latency_ffs|
|lpm_add_sub:587|altshift:carry_ext_latency_ffs|
|lpm_add_sub:587|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:670|
|lpm_add_sub:670|addcore:adder|
|lpm_add_sub:670|addcore:adder|addcore:adder1|
|lpm_add_sub:670|addcore:adder|addcore:adder0|
|lpm_add_sub:670|altshift:result_ext_latency_ffs|
|lpm_add_sub:670|altshift:carry_ext_latency_ffs|
|lpm_add_sub:670|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:753|
|lpm_add_sub:753|addcore:adder|
|lpm_add_sub:753|addcore:adder|addcore:adder1|
|lpm_add_sub:753|addcore:adder|addcore:adder0|
|lpm_add_sub:753|altshift:result_ext_latency_ffs|
|lpm_add_sub:753|altshift:carry_ext_latency_ffs|
|lpm_add_sub:753|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:836|
|lpm_add_sub:836|addcore:adder|
|lpm_add_sub:836|addcore:adder|addcore:adder1|
|lpm_add_sub:836|addcore:adder|addcore:adder0|
|lpm_add_sub:836|altshift:result_ext_latency_ffs|
|lpm_add_sub:836|altshift:carry_ext_latency_ffs|
|lpm_add_sub:836|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:919|
|lpm_add_sub:919|addcore:adder|
|lpm_add_sub:919|addcore:adder|addcore:adder1|
|lpm_add_sub:919|addcore:adder|addcore:adder0|
|lpm_add_sub:919|altshift:result_ext_latency_ffs|
|lpm_add_sub:919|altshift:carry_ext_latency_ffs|
|lpm_add_sub:919|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:1002|
|lpm_add_sub:1002|addcore:adder|
|lpm_add_sub:1002|addcore:adder|addcore:adder1|
|lpm_add_sub:1002|addcore:adder|addcore:adder0|
|lpm_add_sub:1002|altshift:result_ext_latency_ffs|
|lpm_add_sub:1002|altshift:carry_ext_latency_ffs|
|lpm_add_sub:1002|altshift:oflow_ext_latency_ffs|


Device-Specific Information:                           f:\encoder3\encoder.rpt
encoder

***** Logic for device 'encoder' contains errors -- see ERROR SUMMARY.




Device: EPM7128SLC84-15

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff
    MultiVolt I/O                              = OFF



Device-Specific Information:                           f:\encoder3\encoder.rpt
encoder

** ERROR SUMMARY **

Error: Project requires too many (161/128) logic cells
Error: Project requires too many (158/128) shareable expanders


Device-Specific Information:                           f:\encoder3\encoder.rpt
encoder

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     0/16(  0%)   0/ 8(  0%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32     0/16(  0%)   1/ 8( 12%)   0/16(  0%)   0/36(  0%) 
C:    LC33 - LC48     0/16(  0%)   1/ 8( 12%)   0/16(  0%)   0/36(  0%) 
D:    LC49 - LC64     0/16(  0%)   0/ 8(  0%)   0/16(  0%)   0/36(  0%) 
E:    LC65 - LC80     0/16(  0%)   0/ 8(  0%)   0/16(  0%)   0/36(  0%) 
F:    LC81 - LC96     0/16(  0%)   1/ 8( 12%)   0/16(  0%)   0/36(  0%) 
G:   LC97 - LC112     0/16(  0%)   1/ 8( 12%)   0/16(  0%)   0/36(  0%) 
H:  LC113 - LC128     0/16(  0%)   0/ 8(  0%)   0/16(  0%)   0/36(  0%) 


Total dedicated input pins used:                 0/4      (  0%)
Total I/O pins used:                             0/64     (  0%)
Total logic cells used:                          0/128    (  0%)
Total shareable expanders used:                  0/128    (  0%)
Total Turbo logic cells used:                  161/128    (125%)
Total shareable expanders not available (n/a):  21/128    ( 16%)
Average fan-in:                                  9.08
Total fan-in:                                  1462

Total input pins required:                       4
Total fast input logic cells required:           0
Total output pins required:                     17
Total bidirectional pins required:               0
Total reserved pins required                     4
Total logic cells required:                    161
Total flipflops required:                       21
Total product terms required:                  349
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:         137

Synthesized logic cells:                        20/ 128   ( 15%)



Device-Specific Information:                           f:\encoder3\encoder.rpt
encoder

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  ??      -   ??      INPUT  G            0      0   0    0    0    0    0  clk
  ??      -   ??      INPUT               0      0   0    0    0    0    1  QA
  ??      -   ??      INPUT               0      0   0    0    0    0    1  QB
  ??      -   ??      INPUT               0      0   0    0    0   16    0  sel


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:                           f:\encoder3\encoder.rpt
encoder

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name