4encoder.tan.qmsg

编码器信号处理 经过倍频器进行四倍频 后 同时完成鉴相 计数

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register encoder:inst1\|presta\[0\] register encoder:inst1\|db\[15\] 275.71 MHz 3.627 ns Internal " "Info: Clock \"clk\" has Internal fmax of 275.71 MHz between source register \"encoder:inst1\|presta\[0\]\" and destination register \"encoder:inst1\|db\[15\]\" (period= 3.627 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.461 ns + Longest register register " "Info: + Longest register to register delay is 3.461 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns encoder:inst1\|presta\[0\] 1 REG LC_X36_Y24_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y24_N4; Fanout = 3; REG Node = 'encoder:inst1\|presta\[0\]'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { encoder:inst1|presta[0] } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.571 ns) + CELL(0.366 ns) 0.937 ns encoder:inst1\|db\[1\]~1069 2 COMB LC_X35_Y24_N8 41 " "Info: 2: + IC(0.571 ns) + CELL(0.366 ns) = 0.937 ns; Loc. = LC_X35_Y24_N8; Fanout = 41; COMB Node = 'encoder:inst1\|db\[1\]~1069'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.937 ns" { encoder:inst1|presta[0] encoder:inst1|db[1]~1069 } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.116 ns) + CELL(0.344 ns) 2.397 ns encoder:inst1\|db\[3\]~1082 3 COMB LC_X35_Y25_N5 2 " "Info: 3: + IC(1.116 ns) + CELL(0.344 ns) = 2.397 ns; Loc. = LC_X35_Y25_N5; Fanout = 2; COMB Node = 'encoder:inst1\|db\[3\]~1082'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.460 ns" { encoder:inst1|db[1]~1069 encoder:inst1|db[3]~1082 } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 2.455 ns encoder:inst1\|db\[4\]~1081 4 COMB LC_X35_Y25_N6 2 " "Info: 4: + IC(0.000 ns) + CELL(0.058 ns) = 2.455 ns; Loc. = LC_X35_Y25_N6; Fanout = 2; COMB Node = 'encoder:inst1\|db\[4\]~1081'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { encoder:inst1|db[3]~1082 encoder:inst1|db[4]~1081 } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 2.513 ns encoder:inst1\|db\[5\]~1080 5 COMB LC_X35_Y25_N7 2 " "Info: 5: + IC(0.000 ns) + CELL(0.058 ns) = 2.513 ns; Loc. = LC_X35_Y25_N7; Fanout = 2; COMB Node = 'encoder:inst1\|db\[5\]~1080'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { encoder:inst1|db[4]~1081 encoder:inst1|db[5]~1080 } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.058 ns) 2.571 ns encoder:inst1\|db\[6\]~1079 6 COMB LC_X35_Y25_N8 2 " "Info: 6: + IC(0.000 ns) + CELL(0.058 ns) = 2.571 ns; Loc. = LC_X35_Y25_N8; Fanout = 2; COMB Node = 'encoder:inst1\|db\[6\]~1079'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.058 ns" { encoder:inst1|db[5]~1080 encoder:inst1|db[6]~1079 } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.214 ns) 2.785 ns encoder:inst1\|db\[7\]~1078 7 COMB LC_X35_Y25_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.214 ns) = 2.785 ns; Loc. = LC_X35_Y25_N9; Fanout = 6; COMB Node = 'encoder:inst1\|db\[7\]~1078'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.214 ns" { encoder:inst1|db[6]~1079 encoder:inst1|db[7]~1078 } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.098 ns) 2.883 ns encoder:inst1\|db\[12\]~1073 8 COMB LC_X35_Y24_N4 3 " "Info: 8: + IC(0.000 ns) + CELL(0.098 ns) = 2.883 ns; Loc. = LC_X35_Y24_N4; Fanout = 3; COMB Node = 'encoder:inst1\|db\[12\]~1073'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.098 ns" { encoder:inst1|db[7]~1078 encoder:inst1|db[12]~1073 } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.578 ns) 3.461 ns encoder:inst1\|db\[15\] 9 REG LC_X35_Y24_N7 2 " "Info: 9: + IC(0.000 ns) + CELL(0.578 ns) = 3.461 ns; Loc. = LC_X35_Y24_N7; Fanout = 2; REG Node = 'encoder:inst1\|db\[15\]'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.578 ns" { encoder:inst1|db[12]~1073 encoder:inst1|db[15] } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.774 ns ( 51.26 % ) " "Info: Total cell delay = 1.774 ns ( 51.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.687 ns ( 48.74 % ) " "Info: Total interconnect delay = 1.687 ns ( 48.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.461 ns" { encoder:inst1|presta[0] encoder:inst1|db[1]~1069 encoder:inst1|db[3]~1082 encoder:inst1|db[4]~1081 encoder:inst1|db[5]~1080 encoder:inst1|db[6]~1079 encoder:inst1|db[7]~1078 encoder:inst1|db[12]~1073 encoder:inst1|db[15] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "3.461 ns" { encoder:inst1|presta[0] encoder:inst1|db[1]~1069 encoder:inst1|db[3]~1082 encoder:inst1|db[4]~1081 encoder:inst1|db[5]~1080 encoder:inst1|db[6]~1079 encoder:inst1|db[7]~1078 encoder:inst1|db[12]~1073 encoder:inst1|db[15] } { 0.000ns 0.571ns 1.116ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.366ns 0.344ns 0.058ns 0.058ns 0.058ns 0.214ns 0.098ns 0.578ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.897 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 152 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 152; CLK Node = 'clk'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "4encoder.bdf" "" { Schematic "F:/encoder4/4encoder.bdf" { { 88 696 864 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.527 ns) + CELL(0.542 ns) 2.897 ns encoder:inst1\|db\[15\] 2 REG LC_X35_Y24_N7 2 " "Info: 2: + IC(1.527 ns) + CELL(0.542 ns) = 2.897 ns; Loc. = LC_X35_Y24_N7; Fanout = 2; REG Node = 'encoder:inst1\|db\[15\]'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.069 ns" { clk encoder:inst1|db[15] } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.29 % ) " "Info: Total cell delay = 1.370 ns ( 47.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.527 ns ( 52.71 % ) " "Info: Total interconnect delay = 1.527 ns ( 52.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.897 ns" { clk encoder:inst1|db[15] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "2.897 ns" { clk clk~out0 encoder:inst1|db[15] } { 0.000ns 0.000ns 1.527ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.897 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 152 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 152; CLK Node = 'clk'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "4encoder.bdf" "" { Schematic "F:/encoder4/4encoder.bdf" { { 88 696 864 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.527 ns) + CELL(0.542 ns) 2.897 ns encoder:inst1\|presta\[0\] 2 REG LC_X36_Y24_N4 3 " "Info: 2: + IC(1.527 ns) + CELL(0.542 ns) = 2.897 ns; Loc. = LC_X36_Y24_N4; Fanout = 3; REG Node = 'encoder:inst1\|presta\[0\]'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.069 ns" { clk encoder:inst1|presta[0] } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.29 % ) " "Info: Total cell delay = 1.370 ns ( 47.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.527 ns ( 52.71 % ) " "Info: Total interconnect delay = 1.527 ns ( 52.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.897 ns" { clk encoder:inst1|presta[0] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "2.897 ns" { clk clk~out0 encoder:inst1|presta[0] } { 0.000ns 0.000ns 1.527ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.897 ns" { clk encoder:inst1|db[15] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "2.897 ns" { clk clk~out0 encoder:inst1|db[15] } { 0.000ns 0.000ns 1.527ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.897 ns" { clk encoder:inst1|presta[0] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "2.897 ns" { clk clk~out0 encoder:inst1|presta[0] } { 0.000ns 0.000ns 1.527ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.461 ns" { encoder:inst1|presta[0] encoder:inst1|db[1]~1069 encoder:inst1|db[3]~1082 encoder:inst1|db[4]~1081 encoder:inst1|db[5]~1080 encoder:inst1|db[6]~1079 encoder:inst1|db[7]~1078 encoder:inst1|db[12]~1073 encoder:inst1|db[15] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "3.461 ns" { encoder:inst1|presta[0] encoder:inst1|db[1]~1069 encoder:inst1|db[3]~1082 encoder:inst1|db[4]~1081 encoder:inst1|db[5]~1080 encoder:inst1|db[6]~1079 encoder:inst1|db[7]~1078 encoder:inst1|db[12]~1073 encoder:inst1|db[15] } { 0.000ns 0.571ns 1.116ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.366ns 0.344ns 0.058ns 0.058ns 0.058ns 0.214ns 0.098ns 0.578ns } "" } } { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.897 ns" { clk encoder:inst1|db[15] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "2.897 ns" { clk clk~out0 encoder:inst1|db[15] } { 0.000ns 0.000ns 1.527ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.897 ns" { clk encoder:inst1|presta[0] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "2.897 ns" { clk clk~out0 encoder:inst1|presta[0] } { 0.000ns 0.000ns 1.527ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "encoder:inst2\|y\[0\]~en CS0and1 clk 3.413 ns register " "Info: tsu for register \"encoder:inst2\|y\[0\]~en\" (data pin = \"CS0and1\", clock pin = \"clk\") is 3.413 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.300 ns + Longest pin register " "Info: + Longest pin to register delay is 6.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns CS0and1 1 PIN PIN_C8 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_C8; Fanout = 1; PIN Node = 'CS0and1'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CS0and1 } "NODE_NAME" } } { "4encoder.bdf" "" { Schematic "F:/encoder4/4encoder.bdf" { { 432 160 328 448 "CS0and1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.163 ns) + CELL(0.366 ns) 5.616 ns 74138:inst\|18~23 2 COMB LC_X33_Y24_N1 4 " "Info: 2: + IC(4.163 ns) + CELL(0.366 ns) = 5.616 ns; Loc. = LC_X33_Y24_N1; Fanout = 4; COMB Node = '74138:inst\|18~23'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.529 ns" { CS0and1 74138:inst|18~23 } "NODE_NAME" } } { "74138.bdf" "" { Schematic "e:/install/altera/70/quartus/libraries/others/maxplus2/74138.bdf" { { 232 568 632 304 "18" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.319 ns) 6.300 ns encoder:inst2\|y\[0\]~en 3 REG LC_X33_Y24_N6 17 " "Info: 3: + IC(0.365 ns) + CELL(0.319 ns) = 6.300 ns; Loc. = LC_X33_Y24_N6; Fanout = 17; REG Node = 'encoder:inst2\|y\[0\]~en'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.684 ns" { 74138:inst|18~23 encoder:inst2|y[0]~en } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.772 ns ( 28.13 % ) " "Info: Total cell delay = 1.772 ns ( 28.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.528 ns ( 71.87 % ) " "Info: Total interconnect delay = 4.528 ns ( 71.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.300 ns" { CS0and1 74138:inst|18~23 encoder:inst2|y[0]~en } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "6.300 ns" { CS0and1 CS0and1~out0 74138:inst|18~23 encoder:inst2|y[0]~en } { 0.000ns 0.000ns 4.163ns 0.365ns } { 0.000ns 1.087ns 0.366ns 0.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 43 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.897 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 152 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 152; CLK Node = 'clk'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "4encoder.bdf" "" { Schematic "F:/encoder4/4encoder.bdf" { { 88 696 864 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.527 ns) + CELL(0.542 ns) 2.897 ns encoder:inst2\|y\[0\]~en 2 REG LC_X33_Y24_N6 17 " "Info: 2: + IC(1.527 ns) + CELL(0.542 ns) = 2.897 ns; Loc. = LC_X33_Y24_N6; Fanout = 17; REG Node = 'encoder:inst2\|y\[0\]~en'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.069 ns" { clk encoder:inst2|y[0]~en } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.29 % ) " "Info: Total cell delay = 1.370 ns ( 47.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.527 ns ( 52.71 % ) " "Info: Total interconnect delay = 1.527 ns ( 52.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.897 ns" { clk encoder:inst2|y[0]~en } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "2.897 ns" { clk clk~out0 encoder:inst2|y[0]~en } { 0.000ns 0.000ns 1.527ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.300 ns" { CS0and1 74138:inst|18~23 encoder:inst2|y[0]~en } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "6.300 ns" { CS0and1 CS0and1~out0 74138:inst|18~23 encoder:inst2|y[0]~en } { 0.000ns 0.000ns 4.163ns 0.365ns } { 0.000ns 1.087ns 0.366ns 0.319ns } "" } } { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.897 ns" { clk encoder:inst2|y[0]~en } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "2.897 ns" { clk clk~out0 encoder:inst2|y[0]~en } { 0.000ns 0.000ns 1.527ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Y\[14\] encoder:inst2\|y\[0\]~en 10.539 ns register " "Info: tco from clock \"clk\" to destination pin \"Y\[14\]\" through register \"encoder:inst2\|y\[0\]~en\" is 10.539 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.897 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 152 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 152; CLK Node = 'clk'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "4encoder.bdf" "" { Schematic "F:/encoder4/4encoder.bdf" { { 88 696 864 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.527 ns) + CELL(0.542 ns) 2.897 ns encoder:inst2\|y\[0\]~en 2 REG LC_X33_Y24_N6 17 " "Info: 2: + IC(1.527 ns) + CELL(0.542 ns) = 2.897 ns; Loc. = LC_X33_Y24_N6; Fanout = 17; REG Node = 'encoder:inst2\|y\[0\]~en'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.069 ns" { clk encoder:inst2|y[0]~en } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.29 % ) " "Info: Total cell delay = 1.370 ns ( 47.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.527 ns ( 52.71 % ) " "Info: Total interconnect delay = 1.527 ns ( 52.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.897 ns" { clk encoder:inst2|y[0]~en } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "2.897 ns" { clk clk~out0 encoder:inst2|y[0]~en } { 0.000ns 0.000ns 1.527ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 43 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.486 ns + Longest register pin " "Info: + Longest register to pin delay is 7.486 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns encoder:inst2\|y\[0\]~en 1 REG LC_X33_Y24_N6 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y24_N6; Fanout = 17; REG Node = 'encoder:inst2\|y\[0\]~en'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { encoder:inst2|y[0]~en } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.138 ns) + CELL(0.366 ns) 1.504 ns encoder:inst4\|y\[14\]~701 2 COMB LC_X33_Y22_N4 1 " "Info: 2: + IC(1.138 ns) + CELL(0.366 ns) = 1.504 ns; Loc. = LC_X33_Y22_N4; Fanout = 1; COMB Node = 'encoder:inst4\|y\[14\]~701'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.504 ns" { encoder:inst2|y[0]~en encoder:inst4|y[14]~701 } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.955 ns) + CELL(0.366 ns) 2.825 ns encoder:inst4\|y\[14\]~702 3 COMB LC_X33_Y23_N4 1 " "Info: 3: + IC(0.955 ns) + CELL(0.366 ns) = 2.825 ns; Loc. = LC_X33_Y23_N4; Fanout = 1; COMB Node = 'encoder:inst4\|y\[14\]~702'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.321 ns" { encoder:inst4|y[14]~701 encoder:inst4|y[14]~702 } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.257 ns) + CELL(2.404 ns) 7.486 ns Y\[14\] 4 PIN PIN_P10 0 " "Info: 4: + IC(2.257 ns) + CELL(2.404 ns) = 7.486 ns; Loc. = PIN_P10; Fanout = 0; PIN Node = 'Y\[14\]'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.661 ns" { encoder:inst4|y[14]~702 Y[14] } "NODE_NAME" } } { "4encoder.bdf" "" { Schematic "F:/encoder4/4encoder.bdf" { { 16 1144 1320 32 "Y\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.136 ns ( 41.89 % ) " "Info: Total cell delay = 3.136 ns ( 41.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.350 ns ( 58.11 % ) " "Info: Total interconnect delay = 4.350 ns ( 58.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.486 ns" { encoder:inst2|y[0]~en encoder:inst4|y[14]~701 encoder:inst4|y[14]~702 Y[14] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "7.486 ns" { encoder:inst2|y[0]~en encoder:inst4|y[14]~701 encoder:inst4|y[14]~702 Y[14] } { 0.000ns 1.138ns 0.955ns 2.257ns } { 0.000ns 0.366ns 0.366ns 2.404ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.897 ns" { clk encoder:inst2|y[0]~en } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "2.897 ns" { clk clk~out0 encoder:inst2|y[0]~en } { 0.000ns 0.000ns 1.527ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.486 ns" { encoder:inst2|y[0]~en encoder:inst4|y[14]~701 encoder:inst4|y[14]~702 Y[14] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "7.486 ns" { encoder:inst2|y[0]~en encoder:inst4|y[14]~701 encoder:inst4|y[14]~702 Y[14] } { 0.000ns 1.138ns 0.955ns 2.257ns } { 0.000ns 0.366ns 0.366ns 2.404ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "encoder:inst4\|sta\[1\] QA3 clk -1.946 ns register " "Info: th for register \"encoder:inst4\|sta\[1\]\" (data pin = \"QA3\", clock pin = \"clk\") is -1.946 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.913 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.913 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 152 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 152; CLK Node = 'clk'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "4encoder.bdf" "" { Schematic "F:/encoder4/4encoder.bdf" { { 88 696 864 104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.543 ns) + CELL(0.542 ns) 2.913 ns encoder:inst4\|sta\[1\] 2 REG LC_X31_Y21_N4 4 " "Info: 2: + IC(1.543 ns) + CELL(0.542 ns) = 2.913 ns; Loc. = LC_X31_Y21_N4; Fanout = 4; REG Node = 'encoder:inst4\|sta\[1\]'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.085 ns" { clk encoder:inst4|sta[1] } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.03 % ) " "Info: Total cell delay = 1.370 ns ( 47.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.543 ns ( 52.97 % ) " "Info: Total interconnect delay = 1.543 ns ( 52.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.913 ns" { clk encoder:inst4|sta[1] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "2.913 ns" { clk clk~out0 encoder:inst4|sta[1] } { 0.000ns 0.000ns 1.543ns } { 0.000ns 0.828ns 0.542ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.959 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.959 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.972 ns) 0.972 ns QA3 1 PIN PIN_B11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.972 ns) = 0.972 ns; Loc. = PIN_B11; Fanout = 1; PIN Node = 'QA3'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { QA3 } "NODE_NAME" } } { "4encoder.bdf" "" { Schematic "F:/encoder4/4encoder.bdf" { { 632 704 872 648 "QA3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.902 ns) + CELL(0.085 ns) 4.959 ns encoder:inst4\|sta\[1\] 2 REG LC_X31_Y21_N4 4 " "Info: 2: + IC(3.902 ns) + CELL(0.085 ns) = 4.959 ns; Loc. = LC_X31_Y21_N4; Fanout = 4; REG Node = 'encoder:inst4\|sta\[1\]'" {  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.987 ns" { QA3 encoder:inst4|sta[1] } "NODE_NAME" } } { "../encoder3/encoder.vhd" "" { Text "F:/encoder3/encoder.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.057 ns ( 21.31 % ) " "Info: Total cell delay = 1.057 ns ( 21.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.902 ns ( 78.69 % ) " "Info: Total interconnect delay = 3.902 ns ( 78.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.959 ns" { QA3 encoder:inst4|sta[1] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "4.959 ns" { QA3 QA3~out0 encoder:inst4|sta[1] } { 0.000ns 0.000ns 3.902ns } { 0.000ns 0.972ns 0.085ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.913 ns" { clk encoder:inst4|sta[1] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "2.913 ns" { clk clk~out0 encoder:inst4|sta[1] } { 0.000ns 0.000ns 1.543ns } { 0.000ns 0.828ns 0.542ns } "" } } { "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/install/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.959 ns" { QA3 encoder:inst4|sta[1] } "NODE_NAME" } } { "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/install/altera/70/quartus/bin/Technology_Viewer.qrui" "4.959 ns" { QA3 QA3~out0 encoder:inst4|sta[1] } { 0.000ns 0.000ns 3.902ns } { 0.000ns 0.972ns 0.085ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}