4encoder.fit.rpt

编码器信号处理 经过倍频器进行四倍频 后 同时完成鉴相 计数

Fitter report for 4encoder
Sun Mar 29 22:33:47 2009
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Resource Usage Summary
  5. Input Pins
  6. Output Pins
  7. I/O Bank Usage
  8. All Package Pins
  9. Output Pin Default Load For Reported TCO
 10. Fitter Resource Utilization by Entity
 11. Control Signals
 12. Global & Other Fast Signals
 13. Non-Global High Fan-Out Signals
 14. Fitter Device Options
 15. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------+
; Fitter Summary                                                  ;
+-----------------------+-----------------------------------------+
; Fitter Status         ; Failed - Sun Mar 29 22:33:47 2009       ;
; Quartus II Version    ; 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name         ; 4encoder                                ;
; Top-level Entity Name ; 4encoder                                ;
; Family                ; MAX7000S                                ;
; Device                ; EPM7160SLC84-10                         ;
; Timing Models         ; Final                                   ;
; Total macrocells      ; 177 / 160 ( 111 % )                     ;
; Total pins            ; 34 / 64 ( 53 % )                        ;
+-----------------------+-----------------------------------------+


+------------------------------------------------------------------------------+
; Fitter Settings                                                              ;
+--------------------------------------------+-----------------+---------------+
; Option                                     ; Setting         ; Default Value ;
+--------------------------------------------+-----------------+---------------+
; Device                                     ; EPM7160SLC84-10 ;               ;
; Fitter Effort                              ; Standard Fit    ; Auto Fit      ;
; Optimize IOC Register Placement for Timing ; On              ; On            ;
; Limit to One Fitting Attempt               ; Off             ; Off           ;
; Fitter Initial Placement Seed              ; 1               ; 1             ;
; Slow Slew Rate                             ; Off             ; Off           ;
; Use smart compilation                      ; Off             ; Off           ;
+--------------------------------------------+-----------------+---------------+


+-----------------------------------------------------------+
; Fitter Resource Usage Summary                             ;
+-----------------------------------+-----------------------+
; Resource                          ; Usage                 ;
+-----------------------------------+-----------------------+
; Logic cells                       ; 177 / 160 ( 111 % )   ;
; Registers                         ; 152 / 160 ( 95 % )    ;
; Number of pterms used             ; 445                   ;
; User inserted logic elements      ; 0                     ;
; I/O pins                          ; 34 / 64 ( 53 % )      ;
;     -- Clock pins                 ; 0 / 2 ( 0 % )         ;
;     -- Dedicated input pins       ; 0 / 2 ( 0 % )         ;
; Global signals                    ; 1                     ;
; Shareable expanders               ; 36 / 160 ( 23 % )     ;
; Parallel expanders                ; 0 / 150 ( 0 % )       ;
; Cells using turbo bit             ; 0 / 160 ( 0 % )       ;
; Maximum fan-out node              ; clk                   ;
; Maximum fan-out                   ; 152                   ;
; Highest non-global fan-out signal ; encoder:inst1|dir~328 ;
; Highest non-global fan-out        ; 26                    ;
; Total fan-out                     ; 1584                  ;
; Average fan-out                   ; 6.41                  ;
+-----------------------------------+-----------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                   ;
+---------+------------+----------+-----------------------+--------------------+--------+----------------+--------------+----------------------+
; Name    ; Pin #      ; I/O Bank ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; I/O Standard ; Location assigned by ;
+---------+------------+----------+-----------------------+--------------------+--------+----------------+--------------+----------------------+
; A0      ; Unassigned ; --       ; 4                     ; 0                  ; no     ; no             ; TTL          ; Fitter               ;
; A1      ; Unassigned ; --       ; 4                     ; 0                  ; no     ; no             ; TTL          ; Fitter               ;
; A13     ; Unassigned ; --       ; 4                     ; 0                  ; no     ; no             ; TTL          ; Fitter               ;
; A14     ; Unassigned ; --       ; 4                     ; 0                  ; no     ; no             ; TTL          ; Fitter               ;
; CS0and1 ; Unassigned ; --       ; 4                     ; 0                  ; no     ; no             ; TTL          ; Fitter               ;
; QA0     ; Unassigned ; --       ; 1                     ; 0                  ; no     ; no             ; TTL          ; Fitter               ;
; QA1     ; Unassigned ; --       ; 1                     ; 0                  ; no     ; no             ; TTL          ; Fitter               ;
; QA2     ; Unassigned ; --       ; 1                     ; 0                  ; no     ; no             ; TTL          ; Fitter               ;
; QA3     ; Unassigned ; --       ; 1                     ; 0                  ; no     ; no             ; TTL          ; Fitter               ;
; QB0     ; Unassigned ; --       ; 1                     ; 0                  ; no     ; no             ; TTL          ; Fitter               ;
; QB1     ; Unassigned ; --       ; 1                     ; 0                  ; no     ; no             ; TTL          ; Fitter               ;
; QB2     ; Unassigned ; --       ; 1                     ; 0                  ; no     ; no             ; TTL          ; Fitter               ;
; QB3     ; Unassigned ; --       ; 1                     ; 0                  ; no     ; no             ; TTL          ; Fitter               ;
; clk     ; Unassigned ; --       ; 152                   ; 0                  ; yes    ; no             ; TTL          ; Fitter               ;
+---------+------------+----------+-----------------------+--------------------+--------+----------------+--------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                 ;
+-------+------------+----------+-----------------+----------------+------------+---------------+--------------+----------------------+-------+
; Name  ; Pin #      ; I/O Bank ; Output Register ; Slow Slew Rate ; Open Drain ; TRI Primitive ; I/O Standard ; Location assigned by ; Load  ;
+-------+------------+----------+-----------------+----------------+------------+---------------+--------------+----------------------+-------+
; Y[0]  ; Unassigned ; --       ; no              ; no             ; no         ; yes           ; TTL          ; Fitter               ; 10 pF ;
; Y[10] ; Unassigned ; --       ; no              ; no             ; no         ; yes           ; TTL          ; Fitter               ; 10 pF ;
; Y[11] ; Unassigned ; --       ; no              ; no             ; no         ; yes           ; TTL          ; Fitter               ; 10 pF ;
; Y[12] ; Unassigned ; --       ; no              ; no             ; no         ; yes           ; TTL          ; Fitter               ; 10 pF ;
; Y[13] ; Unassigned ; --       ; no              ; no             ; no         ; yes           ; TTL          ; Fitter               ; 10 pF ;
; Y[14] ; Unassigned ; --       ; no              ; no             ; no         ; yes           ; TTL          ; Fitter               ; 10 pF ;