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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PWM_vs_Sigma_Delta_v2 is
generic( N: natural := 4;
Max: natural := 16);
Port ( Clk : in STD_LOGIC;
Scale: in STD_LOGIC;
PCM : in STD_LOGIC_VECTOR (N-1 downto 0);
PWM : out STD_LOGIC;
PPM : out STD_LOGIC); -- or SD
end PWM_vs_Sigma_Delta_v2;
ARCHITECTURE Behavioral of PWM_vs_Sigma_Delta_v2 is
signal PWM_Count: STD_LOGIC_VECTOR (N-1 downto 0) := (others=>'0');
signal Sigma: STD_LOGIC_VECTOR ( N downto 0) := (others=>'0');
signal Delta: STD_LOGIC_VECTOR ( N downto 0) := (others=>'0');
signal Scaled_clk: STD_LOGIC;
begin
process( Clk, Scale)
variable Scalex: integer;
constant Scale100msek: integer := 1; --5000;
constant Scale500msek: integer := 0; --25000;
variable Count: integer range 0 to 50000001 := 0;
begin
if Scale='1' then
Scalex := Scale100msek;
else
Scalex := Scale500msek;
end if;
if rising_edge(Clk)then
if Count>=Scalex then
Scaled_clk <= '1';
Count := 0;
else
Scaled_clk <= '0';
Count := Count+1;
end if;
end if;
end process;
PWM_Generator: process( Clk, PWM_Count, PCM)
begin
if rising_edge(Clk) then
if Scaled_Clk='1' then
if PWM_Count<Max-1 then
PWM_Count <= PWM_Count+1;
else
PWM_Count <= (others => '0');
end if;
end if;
end if;
if PWM_Count<PCM then
PWM <= '1';
else
PWM <= '0';
end if;
end process PWM_Generator;
Delta <= '0'&PCM;
Sigma_Delta_Generator: process( Clk)
begin
if rising_edge(Clk) then
if Scaled_Clk='1' then
if Sigma<Max then
PPM <= '0';
Sigma <= Sigma+Delta;
else
PPM <= '1';
Sigma <= Sigma+Delta-conv_std_logic_vector(Max,N+1);
end if;
end if;
end if;
end process Sigma_Delta_Generator;
end Behavioral;
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