csl_venchal_270.h

dm270 source code

/*   
 *  Copyright 2001 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 */
/******************************************************************************\
*           Copyright (C) 2001 Texas Instruments Incorporated.
*                           All Rights Reserved
*------------------------------------------------------------------------------
* MODULE.NAME... VENC - HAL configuration module
* FILENAME...... /vobs/DSC_RTOS/arm/project/dm270/include/csl/csl_venchal_270.h
* PROJECT....... ARM Chip Support Library
* COMPONENT..... HAL
* IMPORTS....... 
*------------------------------------------------------------------------------
* HISTORY:
*   CREATED:       12/06/2001 
*------------------------------------------------------------------------------
* DESCRIPTION:  (CHIP memory mapped register definitions)
*
*
*
\******************************************************************************/



/*-----------------------------------------------------------------------------------*
* Register Macros for VENC:
*------------------------------------------------------------------------------------*/


/*------------------------------------------------------------------------------*
* Register Macros for VENC VID01 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _VENC_VID01_GET()			_REG_GET(_VENC_VID01_ADDR)
#define _VENC_VID01_SET(Val)			_REG_SET(_VENC_VID01_ADDR, Val)
#define _VENC_VID01_AOI(AND,OR,INV)		_REG_AOI(_VENC_VID01_ADDR,AND,OR,INV)
#define _VENC_VID01_FGET(Field)			_FIELD_GET(_VENC_VID01_ADDR, _VENC_VID01_##Field##)
#define _VENC_VID01_FSET(Field, Val)		_FIELD_SET(_VENC_VID01_ADDR, _VENC_VID01_##Field##, Val)
#define _VENC_VID01_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_VENC_VID01_ADDR, _VENC_VID01_##Field##, AND, OR, INV)

#define _VENC_VID01_NTPLS_SHIFT		(15)
#define _VENC_VID01_NTPLS_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_VID01_NTPLS_SHIFT)
#define _VENC_VID01_NTPLS_MASK			(_VENC_VID01_NTPLS_MK(0x0001u))
#define _VENC_VID01_NTPLS_CLR			(~(_VENC_VID01_NTPLS_MASK))

#define _VENC_VID01_SCMD_SHIFT		(14)
#define _VENC_VID01_SCMD_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_VID01_SCMD_SHIFT)
#define _VENC_VID01_SCMD_MASK			(_VENC_VID01_SCMD_MK(0x0001u))
#define _VENC_VID01_SCMD_CLR			(~(_VENC_VID01_SCMD_MASK))

#define _VENC_VID01_CRCUT_SHIFT		(13)
#define _VENC_VID01_CRCUT_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_VID01_CRCUT_SHIFT)
#define _VENC_VID01_CRCUT_MASK			(_VENC_VID01_CRCUT_MK(0x0001u))
#define _VENC_VID01_CRCUT_CLR			(~(_VENC_VID01_CRCUT_MASK))

#define _VENC_VID01_CBEN_SHIFT		(12)
#define _VENC_VID01_CBEN_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_VID01_CBEN_SHIFT)
#define _VENC_VID01_CBEN_MASK			(_VENC_VID01_CBEN_MK(0x0001u))
#define _VENC_VID01_CBEN_CLR			(~(_VENC_VID01_CBEN_MASK))

#define _VENC_VID01_CBTYP_SHIFT		(11)
#define _VENC_VID01_CBTYP_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_VID01_CBTYP_SHIFT)
#define _VENC_VID01_CBTYP_MASK			(_VENC_VID01_CBTYP_MK(0x0001u))
#define _VENC_VID01_CBTYP_CLR			(~(_VENC_VID01_CBTYP_MASK))

#define _VENC_VID01_SETUP_SHIFT		(10)
#define _VENC_VID01_SETUP_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_VID01_SETUP_SHIFT)
#define _VENC_VID01_SETUP_MASK			(_VENC_VID01_SETUP_MK(0x0001u))
#define _VENC_VID01_SETUP_CLR			(~(_VENC_VID01_SETUP_MASK))

#define _VENC_VID01_RGBFLT_SHIFT		(8)
#define _VENC_VID01_RGBFLT_MK(n)		(((Uint16)(n) & 0x0003u) << _VENC_VID01_RGBFLT_SHIFT)
#define _VENC_VID01_RGBFLT_MASK			(_VENC_VID01_RGBFLT_MK(0x0003u))
#define _VENC_VID01_RGBFLT_CLR			(~(_VENC_VID01_RGBFLT_MASK))

#define _VENC_VID01_YFLT_SHIFT		(7)
#define _VENC_VID01_YFLT_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_VID01_YFLT_SHIFT)
#define _VENC_VID01_YFLT_MASK			(_VENC_VID01_YFLT_MK(0x0001u))
#define _VENC_VID01_YFLT_CLR			(~(_VENC_VID01_YFLT_MASK))

#define _VENC_VID01_DAPD_SHIFT		(6)
#define _VENC_VID01_DAPD_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_VID01_DAPD_SHIFT)
#define _VENC_VID01_DAPD_MASK			(_VENC_VID01_DAPD_MK(0x0001u))
#define _VENC_VID01_DAPD_CLR			(~(_VENC_VID01_DAPD_MASK))

#define _VENC_VID01_DAOE_SHIFT		(5)
#define _VENC_VID01_DAOE_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_VID01_DAOE_SHIFT)
#define _VENC_VID01_DAOE_MASK			(_VENC_VID01_DAOE_MK(0x0001u))
#define _VENC_VID01_DAOE_CLR			(~(_VENC_VID01_DAOE_MASK))

#define _VENC_VID01_VOUT_SHIFT		(2)
#define _VENC_VID01_VOUT_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_VID01_VOUT_SHIFT)
#define _VENC_VID01_VOUT_MASK			(_VENC_VID01_VOUT_MK(0x0001u))
#define _VENC_VID01_VOUT_CLR			(~(_VENC_VID01_VOUT_MASK))

#define _VENC_VID01_BLANK_SHIFT		(1)
#define _VENC_VID01_BLANK_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_VID01_BLANK_SHIFT)
#define _VENC_VID01_BLANK_MASK			(_VENC_VID01_BLANK_MK(0x0001u))
#define _VENC_VID01_BLANK_CLR			(~(_VENC_VID01_BLANK_MASK))

#define _VENC_VID01_VENC_SHIFT		(0)
#define _VENC_VID01_VENC_MK(n)		((Uint16)(n) & 0x0001u) 
#define _VENC_VID01_VENC_MASK			(_VENC_VID01_VENC_MK(0x0001u))
#define _VENC_VID01_VENC_CLR			(~(_VENC_VID01_VENC_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for VENC VID02 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _VENC_VID02_GET()			_REG_GET(_VENC_VID02_ADDR)
#define _VENC_VID02_SET(Val)			_REG_SET(_VENC_VID02_ADDR, Val)
#define _VENC_VID02_AOI(AND,OR,INV)		_REG_AOI(_VENC_VID02_ADDR,AND,OR,INV)
#define _VENC_VID02_FGET(Field)			_FIELD_GET(_VENC_VID02_ADDR, _VENC_VID02_##Field##)
#define _VENC_VID02_FSET(Field, Val)		_FIELD_SET(_VENC_VID02_ADDR, _VENC_VID02_##Field##, Val)
#define _VENC_VID02_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_VENC_VID02_ADDR, _VENC_VID02_##Field##, AND, OR, INV)

#define _VENC_VID02_VIMD_SHIFT		(14)
#define _VENC_VID02_VIMD_MK(n)		(((Uint16)(n) & 0x0003u) << _VENC_VID02_VIMD_SHIFT)
#define _VENC_VID02_VIMD_MASK			(_VENC_VID02_VIMD_MK(0x0003u))
#define _VENC_VID02_VIMD_CLR			(~(_VENC_VID02_VIMD_MASK))

#define _VENC_VID02_INLVL_SHIFT		(13)
#define _VENC_VID02_INLVL_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_VID02_INLVL_SHIFT)
#define _VENC_VID02_INLVL_MASK			(_VENC_VID02_INLVL_MK(0x0001u))
#define _VENC_VID02_INLVL_CLR			(~(_VENC_VID02_INLVL_MASK))

#define _VENC_VID02_SYSW_SHIFT		(12)
#define _VENC_VID02_SYSW_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_VID02_SYSW_SHIFT)
#define _VENC_VID02_SYSW_MASK			(_VENC_VID02_SYSW_MK(0x0001u))
#define _VENC_VID02_SYSW_CLR			(~(_VENC_VID02_SYSW_MASK))

#define _VENC_VID02_VSSW_SHIFT		(11)
#define _VENC_VID02_VSSW_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_VID02_VSSW_SHIFT)
#define _VENC_VID02_VSSW_MASK			(_VENC_VID02_VSSW_MK(0x0001u))
#define _VENC_VID02_VSSW_CLR			(~(_VENC_VID02_VSSW_MASK))

#define _VENC_VID02_SYNE_SHIFT		(10)
#define _VENC_VID02_SYNE_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_VID02_SYNE_SHIFT)
#define _VENC_VID02_SYNE_MASK			(_VENC_VID02_SYNE_MK(0x0001u))
#define _VENC_VID02_SYNE_CLR			(~(_VENC_VID02_SYNE_MASK))

#define _VENC_VID02_BREN_SHIFT		(9)
#define _VENC_VID02_BREN_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_VID02_BREN_SHIFT)
#define _VENC_VID02_BREN_MASK			(_VENC_VID02_BREN_MK(0x0001u))
#define _VENC_VID02_BREN_CLR			(~(_VENC_VID02_BREN_MASK))

#define _VENC_VID02_BRPL_SHIFT		(8)
#define _VENC_VID02_BRPL_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_VID02_BRPL_SHIFT)
#define _VENC_VID02_BRPL_MASK			(_VENC_VID02_BRPL_MK(0x0001u))
#define _VENC_VID02_BRPL_CLR			(~(_VENC_VID02_BRPL_MASK))

#define _VENC_VID02_BRWDTH_SHIFT		(0)
#define _VENC_VID02_BRWDTH_MK(n)		((Uint16)(n) & 0x00ffu) 
#define _VENC_VID02_BRWDTH_MASK			(_VENC_VID02_BRWDTH_MK(0x00ffu))
#define _VENC_VID02_BRWDTH_CLR			(~(_VENC_VID02_BRWDTH_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for VENC DLCD1 register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _VENC_DLCD1_GET()			_REG_GET(_VENC_DLCD1_ADDR)
#define _VENC_DLCD1_SET(Val)			_REG_SET(_VENC_DLCD1_ADDR, Val)
#define _VENC_DLCD1_AOI(AND,OR,INV)		_REG_AOI(_VENC_DLCD1_ADDR,AND,OR,INV)
#define _VENC_DLCD1_FGET(Field)			_FIELD_GET(_VENC_DLCD1_ADDR, _VENC_DLCD1_##Field##)
#define _VENC_DLCD1_FSET(Field, Val)		_FIELD_SET(_VENC_DLCD1_ADDR, _VENC_DLCD1_##Field##, Val)
#define _VENC_DLCD1_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_VENC_DLCD1_ADDR, _VENC_DLCD1_##Field##, AND, OR, INV)

#define _VENC_DLCD1_DRGBE_SHIFT		(15)
#define _VENC_DLCD1_DRGBE_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_DLCD1_DRGBE_SHIFT)
#define _VENC_DLCD1_DRGBE_MASK			(_VENC_DLCD1_DRGBE_MK(0x0001u))
#define _VENC_DLCD1_DRGBE_CLR			(~(_VENC_DLCD1_DRGBE_MASK))

#define _VENC_DLCD1_VPL_SHIFT		(14)
#define _VENC_DLCD1_VPL_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_DLCD1_VPL_SHIFT)
#define _VENC_DLCD1_VPL_MASK			(_VENC_DLCD1_VPL_MK(0x0001u))
#define _VENC_DLCD1_VPL_CLR			(~(_VENC_DLCD1_VPL_MASK))

#define _VENC_DLCD1_HPL_SHIFT		(13)
#define _VENC_DLCD1_HPL_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_DLCD1_HPL_SHIFT)
#define _VENC_DLCD1_HPL_MASK			(_VENC_DLCD1_HPL_MK(0x0001u))
#define _VENC_DLCD1_HPL_CLR			(~(_VENC_DLCD1_HPL_MASK))

#define _VENC_DLCD1_LRCE_SHIFT		(11)
#define _VENC_DLCD1_LRCE_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_DLCD1_LRCE_SHIFT)
#define _VENC_DLCD1_LRCE_MASK			(_VENC_DLCD1_LRCE_MK(0x0001u))
#define _VENC_DLCD1_LRCE_CLR			(~(_VENC_DLCD1_LRCE_MASK))

#define _VENC_DLCD1_EXLID_SHIFT		(10)
#define _VENC_DLCD1_EXLID_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_DLCD1_EXLID_SHIFT)
#define _VENC_DLCD1_EXLID_MASK			(_VENC_DLCD1_EXLID_MK(0x0001u))
#define _VENC_DLCD1_EXLID_CLR			(~(_VENC_DLCD1_EXLID_MASK))

#define _VENC_DLCD1_EXIDP_SHIFT		(9)
#define _VENC_DLCD1_EXIDP_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_DLCD1_EXIDP_SHIFT)
#define _VENC_DLCD1_EXIDP_MASK			(_VENC_DLCD1_EXIDP_MK(0x0001u))
#define _VENC_DLCD1_EXIDP_CLR			(~(_VENC_DLCD1_EXIDP_MASK))

#define _VENC_DLCD1_IRONM_SHIFT		(8)
#define _VENC_DLCD1_IRONM_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_DLCD1_IRONM_SHIFT)
#define _VENC_DLCD1_IRONM_MASK			(_VENC_DLCD1_IRONM_MK(0x0001u))
#define _VENC_DLCD1_IRONM_CLR			(~(_VENC_DLCD1_IRONM_MASK))

#define _VENC_DLCD1_RGBF_SHIFT		(7)
#define _VENC_DLCD1_RGBF_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_DLCD1_RGBF_SHIFT)
#define _VENC_DLCD1_RGBF_MASK			(_VENC_DLCD1_RGBF_MK(0x0001u))
#define _VENC_DLCD1_RGBF_CLR			(~(_VENC_DLCD1_RGBF_MASK))

#define _VENC_DLCD1_LINID_SHIFT		(6)
#define _VENC_DLCD1_LINID_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_DLCD1_LINID_SHIFT)