csl_venchal_270.h

来自「dm270 source code」· C头文件代码 · 共 1,123 行 · 第 1/5 页
1,123 行
#define _VENC_REC656_CBCR_SHIFT		(2)
#define _VENC_REC656_CBCR_MK(n)		(((Uint16)(n) & 0x0003u) << _VENC_REC656_CBCR_SHIFT)
#define _VENC_REC656_CBCR_MASK			(_VENC_REC656_CBCR_MK(0x0003u))
#define _VENC_REC656_CBCR_CLR			(~(_VENC_REC656_CBCR_MASK))

#define _VENC_REC656_SYNCE_SHIFT		(1)
#define _VENC_REC656_SYNCE_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_REC656_SYNCE_SHIFT)
#define _VENC_REC656_SYNCE_MASK			(_VENC_REC656_SYNCE_MK(0x0001u))
#define _VENC_REC656_SYNCE_CLR			(~(_VENC_REC656_SYNCE_MASK))

#define _VENC_REC656_RECE_SHIFT		(0)
#define _VENC_REC656_RECE_MK(n)		((Uint16)(n) & 0x0001u) 
#define _VENC_REC656_RECE_MASK			(_VENC_REC656_RECE_MK(0x0001u))
#define _VENC_REC656_RECE_CLR			(~(_VENC_REC656_RECE_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for VENC EPSON_LCD register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _VENC_EPSON_LCD_GET()			_REG_GET(_VENC_EPSON_LCD_ADDR)
#define _VENC_EPSON_LCD_SET(Val)			_REG_SET(_VENC_EPSON_LCD_ADDR, Val)
#define _VENC_EPSON_LCD_AOI(AND,OR,INV)		_REG_AOI(_VENC_EPSON_LCD_ADDR,AND,OR,INV)
#define _VENC_EPSON_LCD_FGET(Field)			_FIELD_GET(_VENC_EPSON_LCD_ADDR, _VENC_EPSON_LCD_##Field##)
#define _VENC_EPSON_LCD_FSET(Field, Val)		_FIELD_SET(_VENC_EPSON_LCD_ADDR, _VENC_EPSON_LCD_##Field##, Val)
#define _VENC_EPSON_LCD_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_VENC_EPSON_LCD_ADDR, _VENC_EPSON_LCD_##Field##, AND, OR, INV)

#define _VENC_EPSON_LCD_EPVM_SHIFT		(11)
#define _VENC_EPSON_LCD_EPVM_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_EPSON_LCD_EPVM_SHIFT)
#define _VENC_EPSON_LCD_EPVM_MASK			(_VENC_EPSON_LCD_EPVM_MK(0x0001u))
#define _VENC_EPSON_LCD_EPVM_CLR			(~(_VENC_EPSON_LCD_EPVM_MASK))

#define _VENC_EPSON_LCD_EPSYSC_SHIFT		(10)
#define _VENC_EPSON_LCD_EPSYSC_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_EPSON_LCD_EPSYSC_SHIFT)
#define _VENC_EPSON_LCD_EPSYSC_MASK			(_VENC_EPSON_LCD_EPSYSC_MK(0x0001u))
#define _VENC_EPSON_LCD_EPSYSC_CLR			(~(_VENC_EPSON_LCD_EPSYSC_MASK))

#define _VENC_EPSON_LCD_EPRGBR_SHIFT		(9)
#define _VENC_EPSON_LCD_EPRGBR_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_EPSON_LCD_EPRGBR_SHIFT)
#define _VENC_EPSON_LCD_EPRGBR_MASK			(_VENC_EPSON_LCD_EPRGBR_MK(0x0001u))
#define _VENC_EPSON_LCD_EPRGBR_CLR			(~(_VENC_EPSON_LCD_EPRGBR_MASK))

#define _VENC_EPSON_LCD_EPYFS_SHIFT		(5)
#define _VENC_EPSON_LCD_EPYFS_MK(n)		(((Uint16)(n) & 0x0003u) << _VENC_EPSON_LCD_EPYFS_SHIFT)
#define _VENC_EPSON_LCD_EPYFS_MASK			(_VENC_EPSON_LCD_EPYFS_MK(0x0003u))
#define _VENC_EPSON_LCD_EPYFS_CLR			(~(_VENC_EPSON_LCD_EPYFS_MASK))

#define _VENC_EPSON_LCD_EP18DBT_SHIFT		(4)
#define _VENC_EPSON_LCD_EP18DBT_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_EPSON_LCD_EP18DBT_SHIFT)
#define _VENC_EPSON_LCD_EP18DBT_MASK			(_VENC_EPSON_LCD_EP18DBT_MK(0x0001u))
#define _VENC_EPSON_LCD_EP18DBT_CLR			(~(_VENC_EPSON_LCD_EP18DBT_MASK))

#define _VENC_EPSON_LCD_GCPRD_SHIFT		(3)
#define _VENC_EPSON_LCD_GCPRD_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_EPSON_LCD_GCPRD_SHIFT)
#define _VENC_EPSON_LCD_GCPRD_MASK			(_VENC_EPSON_LCD_GCPRD_MK(0x0001u))
#define _VENC_EPSON_LCD_GCPRD_CLR			(~(_VENC_EPSON_LCD_GCPRD_MASK))

#define _VENC_EPSON_LCD_GCPRU_SHIFT		(2)
#define _VENC_EPSON_LCD_GCPRU_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_EPSON_LCD_GCPRU_SHIFT)
#define _VENC_EPSON_LCD_GCPRU_MASK			(_VENC_EPSON_LCD_GCPRU_MK(0x0001u))
#define _VENC_EPSON_LCD_GCPRU_CLR			(~(_VENC_EPSON_LCD_GCPRU_MASK))

#define _VENC_EPSON_LCD_GCPSL_SHIFT		(0)
#define _VENC_EPSON_LCD_GCPSL_MK(n)		((Uint16)(n) & 0x0003u) 
#define _VENC_EPSON_LCD_GCPSL_MASK			(_VENC_EPSON_LCD_GCPSL_MK(0x0003u))
#define _VENC_EPSON_LCD_GCPSL_CLR			(~(_VENC_EPSON_LCD_GCPSL_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for VENC GCPDATA register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _VENC_GCPDATA_GET()			_REG_GET(_VENC_GCPDATA_ADDR)
#define _VENC_GCPDATA_SET(Val)			_REG_SET(_VENC_GCPDATA_ADDR, Val)
#define _VENC_GCPDATA_AOI(AND,OR,INV)		_REG_AOI(_VENC_GCPDATA_ADDR,AND,OR,INV)



/*------------------------------------------------------------------------------*
* Register Macros for VENC CASIO register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _VENC_CASIO_GET()			_REG_GET(_VENC_CASIO_ADDR)
#define _VENC_CASIO_SET(Val)			_REG_SET(_VENC_CASIO_ADDR, Val)
#define _VENC_CASIO_AOI(AND,OR,INV)		_REG_AOI(_VENC_CASIO_ADDR,AND,OR,INV)
#define _VENC_CASIO_FGET(Field)			_FIELD_GET(_VENC_CASIO_ADDR, _VENC_CASIO_##Field##)
#define _VENC_CASIO_FSET(Field, Val)		_FIELD_SET(_VENC_CASIO_ADDR, _VENC_CASIO_##Field##, Val)
#define _VENC_CASIO_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_VENC_CASIO_ADDR, _VENC_CASIO_##Field##, AND, OR, INV)

#define _VENC_CASIO_CGRES_SHIFT		(5)
#define _VENC_CASIO_CGRES_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_CASIO_CGRES_SHIFT)
#define _VENC_CASIO_CGRES_MASK			(_VENC_CASIO_CGRES_MK(0x0001u))
#define _VENC_CASIO_CGRES_CLR			(~(_VENC_CASIO_CGRES_MASK))

#define _VENC_CASIO_CDM_SHIFT		(4)
#define _VENC_CASIO_CDM_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_CASIO_CDM_SHIFT)
#define _VENC_CASIO_CDM_MASK			(_VENC_CASIO_CDM_MK(0x0001u))
#define _VENC_CASIO_CDM_CLR			(~(_VENC_CASIO_CDM_MASK))

#define _VENC_CASIO_CRIT_SHIFT		(3)
#define _VENC_CASIO_CRIT_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_CASIO_CRIT_SHIFT)
#define _VENC_CASIO_CRIT_MASK			(_VENC_CASIO_CRIT_MK(0x0001u))
#define _VENC_CASIO_CRIT_CLR			(~(_VENC_CASIO_CRIT_MASK))

#define _VENC_CASIO_CSTB_SHIFT		(2)
#define _VENC_CASIO_CSTB_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_CASIO_CSTB_SHIFT)
#define _VENC_CASIO_CSTB_MASK			(_VENC_CASIO_CSTB_MK(0x0001u))
#define _VENC_CASIO_CSTB_CLR			(~(_VENC_CASIO_CSTB_MASK))

#define _VENC_CASIO_CLS_SHIFT		(0)
#define _VENC_CASIO_CLS_MK(n)		((Uint16)(n) & 0x0003u) 
#define _VENC_CASIO_CLS_MASK			(_VENC_CASIO_CLS_MK(0x0003u))
#define _VENC_CASIO_CLS_CLR			(~(_VENC_CASIO_CLS_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for VENC DOUTCTL register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _VENC_DOUTCTL_GET()			_REG_GET(_VENC_DOUTCTL_ADDR)
#define _VENC_DOUTCTL_SET(Val)			_REG_SET(_VENC_DOUTCTL_ADDR, Val)
#define _VENC_DOUTCTL_AOI(AND,OR,INV)		_REG_AOI(_VENC_DOUTCTL_ADDR,AND,OR,INV)
#define _VENC_DOUTCTL_FGET(Field)			_FIELD_GET(_VENC_DOUTCTL_ADDR, _VENC_DOUTCTL_##Field##)
#define _VENC_DOUTCTL_FSET(Field, Val)		_FIELD_SET(_VENC_DOUTCTL_ADDR, _VENC_DOUTCTL_##Field##, Val)
#define _VENC_DOUTCTL_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_VENC_DOUTCTL_ADDR, _VENC_DOUTCTL_##Field##, AND, OR, INV)

#define _VENC_DOUTCTL_DOF_SHIFT		(12)
#define _VENC_DOUTCTL_DOF_MK(n)		(((Uint16)(n) & 0x0003u) << _VENC_DOUTCTL_DOF_SHIFT)
#define _VENC_DOUTCTL_DOF_MASK			(_VENC_DOUTCTL_DOF_MK(0x0003u))
#define _VENC_DOUTCTL_DOF_CLR			(~(_VENC_DOUTCTL_DOF_MASK))

#define _VENC_DOUTCTL_VCLKS_SHIFT		(11)
#define _VENC_DOUTCTL_VCLKS_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_DOUTCTL_VCLKS_SHIFT)
#define _VENC_DOUTCTL_VCLKS_MASK			(_VENC_DOUTCTL_VCLKS_MK(0x0001u))
#define _VENC_DOUTCTL_VCLKS_CLR			(~(_VENC_DOUTCTL_VCLKS_MASK))

#define _VENC_DOUTCTL_ESGEN_SHIFT		(10)
#define _VENC_DOUTCTL_ESGEN_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_DOUTCTL_ESGEN_SHIFT)
#define _VENC_DOUTCTL_ESGEN_MASK			(_VENC_DOUTCTL_ESGEN_MK(0x0001u))
#define _VENC_DOUTCTL_ESGEN_CLR			(~(_VENC_DOUTCTL_ESGEN_MASK))

#define _VENC_DOUTCTL_EFIV_SHIFT		(9)
#define _VENC_DOUTCTL_EFIV_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_DOUTCTL_EFIV_SHIFT)
#define _VENC_DOUTCTL_EFIV_MASK			(_VENC_DOUTCTL_EFIV_MK(0x0001u))
#define _VENC_DOUTCTL_EFIV_CLR			(~(_VENC_DOUTCTL_EFIV_MASK))

#define _VENC_DOUTCTL_EFEN_SHIFT		(8)
#define _VENC_DOUTCTL_EFEN_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_DOUTCTL_EFEN_SHIFT)
#define _VENC_DOUTCTL_EFEN_MASK			(_VENC_DOUTCTL_EFEN_MK(0x0001u))
#define _VENC_DOUTCTL_EFEN_CLR			(~(_VENC_DOUTCTL_EFEN_MASK))

#define _VENC_DOUTCTL_ESYIV_SHIFT		(7)
#define _VENC_DOUTCTL_ESYIV_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_DOUTCTL_ESYIV_SHIFT)
#define _VENC_DOUTCTL_ESYIV_MASK			(_VENC_DOUTCTL_ESYIV_MK(0x0001u))
#define _VENC_DOUTCTL_ESYIV_CLR			(~(_VENC_DOUTCTL_ESYIV_MASK))

#define _VENC_DOUTCTL_ESYEN_SHIFT		(6)
#define _VENC_DOUTCTL_ESYEN_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_DOUTCTL_ESYEN_SHIFT)
#define _VENC_DOUTCTL_ESYEN_MASK			(_VENC_DOUTCTL_ESYEN_MK(0x0001u))
#define _VENC_DOUTCTL_ESYEN_CLR			(~(_VENC_DOUTCTL_ESYEN_MASK))

#define _VENC_DOUTCTL_Y16O_SHIFT		(4)
#define _VENC_DOUTCTL_Y16O_MK(n)		(((Uint16)(n) & 0x0003u) << _VENC_DOUTCTL_Y16O_SHIFT)
#define _VENC_DOUTCTL_Y16O_MASK			(_VENC_DOUTCTL_Y16O_MK(0x0003u))
#define _VENC_DOUTCTL_Y16O_CLR			(~(_VENC_DOUTCTL_Y16O_MASK))

#define _VENC_DOUTCTL_DOIV_SHIFT		(3)
#define _VENC_DOUTCTL_DOIV_MK(n)		(((Uint16)(n) & 0x0001u) << _VENC_DOUTCTL_DOIV_SHIFT)
#define _VENC_DOUTCTL_DOIV_MASK			(_VENC_DOUTCTL_DOIV_MK(0x0001u))
#define _VENC_DOUTCTL_DOIV_CLR			(~(_VENC_DOUTCTL_DOIV_MASK))

#define _VENC_DOUTCTL_DOMD_SHIFT		(1)
#define _VENC_DOUTCTL_DOMD_MK(n)		(((Uint16)(n) & 0x0003u) << _VENC_DOUTCTL_DOMD_SHIFT)
#define _VENC_DOUTCTL_DOMD_MASK			(_VENC_DOUTCTL_DOMD_MK(0x0003u))
#define _VENC_DOUTCTL_DOMD_CLR			(~(_VENC_DOUTCTL_DOMD_MASK))

#define _VENC_DOUTCTL_DODIS_SHIFT		(0)
#define _VENC_DOUTCTL_DODIS_MK(n)		((Uint16)(n) & 0x0001u) 
#define _VENC_DOUTCTL_DODIS_MASK			(_VENC_DOUTCTL_DODIS_MK(0x0001u))
#define _VENC_DOUTCTL_DODIS_CLR			(~(_VENC_DOUTCTL_DODIS_MASK))



/*------------------------------------------------------------------------------*
* Register Macros for VENC SGHSYNP register :
*                                                                                    
*                                                                                    
*                                                                                    
*---------------------------------------------------------------------------------*/

#define _VENC_SGHSYNP_GET()			_REG_GET(_VENC_SGHSYNP_ADDR)
#define _VENC_SGHSYNP_SET(Val)			_REG_SET(_VENC_SGHSYNP_ADDR, Val)
#define _VENC_SGHSYNP_AOI(AND,OR,INV)		_REG_AOI(_VENC_SGHSYNP_ADDR,AND,OR,INV)
#define _VENC_SGHSYNP_FGET(Field)			_FIELD_GET(_VENC_SGHSYNP_ADDR, _VENC_SGHSYNP_##Field##)
#define _VENC_SGHSYNP_FSET(Field, Val)		_FIELD_SET(_VENC_SGHSYNP_ADDR, _VENC_SGHSYNP_##Field##, Val)
#define _VENC_SGHSYNP_FAOI(Field, AND, OR, INV)	_FIELD_AOI(_VENC_SGHSYNP_ADDR, _VENC_SGHSYNP_##Field##, AND, OR, INV)

#define _VENC_SGHSYNP_SGVP_SHIFT		(12)
#define _VENC_SGHSYNP_SGVP_MK(n)		(((Uint16)(n) & 0x000fu) << _VENC_SGHSYNP_SGVP_SHIFT)
#define _VENC_SGHSYNP_SGVP_MASK			(_VENC_SGHSYNP_SGVP_MK(0x000fu))
#define _VENC_SGHSYNP_SGVP_CLR			(~(_VENC_SGHSYNP_SGVP_MASK))

#define _VENC_SGHSYNP_SGHP_SHIFT		(0)
#define _VENC_SGHSYNP_SGHP_MK(n)		((Uint16)(n) & 0x01ffu) 
#define _VENC_SGHSYNP_SGHP_MASK			(_VENC_SGHSYNP_SGHP_MK(0x01ffu))
#define _VENC_SGHSYNP_SGHP_CLR			(~(_VENC_SGHSYNP_SGHP_MASK))
csl_venchal_270.h - 源码说明

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