dg408.vhd

FPGA对模拟开关DG408的控制程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DG408 is
port(	inclk0_sig :in std_logic;
		clkout0	   :out std_logic;
		en,A0,A1,A2:out std_logic);
end DG408;

architecture Behavioral of DG408 is
signal clkscan0:std_logic;
signal clk:std_logic;
component PLL
	PORT(inclk0		: IN STD_LOGIC  := '0';
		  c0		: OUT STD_LOGIC );
end component;

begin
PLL_inst : PLL PORT MAP (inclk0=>inclk0_sig,c0=>clk);

process(clk,clkscan0)							--100ksps   2MHz
variable cnt0:integer range 0 to 49;
begin
   if clk'event and clk='1' then cnt0:=cnt0+1;
      if cnt0<=24 then clkscan0<='0';
      elsif cnt0<=49 then clkscan0<='1';
      else cnt0:=0;clkscan0<='0';
      end if;
   end if;
       clkout0<=clkscan0;
end process;

process(clkscan0)
variable cnt1:integer range 0 to 1999999;
begin
	if clkscan0'event and clkscan0='1' then cnt1:=cnt1+1;
		if 	  cnt1=999994  then en<='0';							-- DG408关断
		elsif cnt1=999999  then A0<='1';A1<='1';A2<='1';
		elsif cnt1=1999994 then en<='1';							-- DG408开启
		elsif cnt1=1999999 then A0<='0';A1<='0';A2<='0';cnt1:=0;	-- 通道1导通
		end if;
	end if;
	end process;
end Behavioral;