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📄 controller.vhd

📁 FPGA对TLC0831的控制程序
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-- 名称:TLC0831控制模块v1.0
-- 功能:实现对TLC0831的相应控制,并接受TLC0831返回的转换信号
-- 日期:2008.12.3
-- 修改笔记:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity controller is
port( 	d:in std_logic_vector(7 downto 0);     								 -- ADC0809输出的采样数据
		clk,eoc:in std_logic;       		 								 -- clk为系统时钟,eoc为转换结束信号
		clk1,start,ale,en:out std_logic;         							 -- ADC0809控制信号
 		abc_in:in std_logic_vector(2 downto 0);   							 -- 模拟选通信号
		abc_out:out std_logic_vector(2 downto 0); 							 -- ADC0809模拟信号选通信号
		q:out std_logic_vector(7 downto 0));     							 -- 送至8个并排数码管信号
end controller;

architecture behav of controller is 
type states is ( st0,st1,st2,st3,st4,st5,st6);          			 --定义各状态的子类型
signal current_state,next_state:states:=st0;
signal regl:std_logic_vector(7 downto 0);                				 --中间数据寄存信号
signal qq:std_logic_vector(7 downto 0);
begin
com:process(current_state,eoc)                          					 --规定各种状态的转换方式
begin
  case current_state is
  when st0=>next_state<=st1;ale<='0';start<='0';en<='0';
  when st1=>next_state<=st2;ale<='1';start<='0';en<='0';
  when st2=>next_state<=st3;ale<='0';start<='1';en<='0';
  when st3=>ale<='0';start<='0';en<='0';
        if eoc='1' then next_state<=st3;                 				 --检测EOC的下降沿
        else next_state<=st4;
        end if;  
  when st4=>ale<='0';start<='0';en<='0';
        if eoc='0' then next_state<=st4;                  				 --检测EOC的上升沿
else next_state<=st5;
end if;
  when st5=>next_state<=st6;ale<='0';start<='0';en<='1';
  when st6=>next_state<=st0;ale<='0';start<='0';en<='1';regl<=d;
  when others=> next_state<=st0;ale<='0';start<='0';en<='0';
  end case;
end process;
clock:process(clk)                											 --对系统时钟进行分频,得到ADC转换工作时钟
begin
 if clk'event and clk='1' then qq<=qq+1;             						 --在clk1的上升沿,转换至下一状态
if QQ="01111111" THEN clk1<='1';current_state <=next_state;    
elsif qq<="01111111" then clk1<='0';
end if;
end if;
end process;
q<=regl; abc_out<=abc_in;  
end behav;


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