decl7s.rpt

共阴极七段数码管的译码程序

8    -> * * * * * * * * * * * * * * * * | * * | <-- A3
LC5  -> - - - - - * - - - * - - - - - - | - * | <-- ~377~1
LC1  -> - - - - * - - - - - * - - - - - | - * | <-- ~413~1
LC12 -> - - * - - - - - - - - - - * - - | - * | <-- ~479~1
LC4  -> - * - - - - - - - - - - - - * - | - * | <-- ~512~1
LC8  -> * - - - - - - - - - - - - - - * | - * | <-- ~545~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:       e:\eda_all\quartusii_eda(hust)\1\decl7s.rpt
decl7s

** EQUATIONS **

A0       : INPUT;
A1       : INPUT;
A2       : INPUT;
A3       : INPUT;

-- Node name is 'LED7S0' 
-- Equation name is 'LED7S0', location is LC026, type is output.
 LED7S0  = LCELL( _EQ001 $  _EQ002);
  _EQ001 =  _LC008 &  _X001;
  _X001  = EXP(!A0 & !A1 & !A2 & !A3);
  _EQ002 = !A0 & !A1 & !A2 & !A3;

-- Node name is 'LED7S1' 
-- Equation name is 'LED7S1', location is LC028, type is output.
 LED7S1  = LCELL( _EQ003 $  _EQ004);
  _EQ003 =  _LC004 &  _X001;
  _X001  = EXP(!A0 & !A1 & !A2 & !A3);
  _EQ004 = !A0 & !A1 & !A2 & !A3;

-- Node name is 'LED7S2' 
-- Equation name is 'LED7S2', location is LC029, type is output.
 LED7S2  = LCELL( _EQ005 $  _EQ006);
  _EQ005 =  _LC012 &  _X001;
  _X001  = EXP(!A0 & !A1 & !A2 & !A3);
  _EQ006 = !A0 & !A1 & !A2 & !A3;

-- Node name is 'LED7S3' 
-- Equation name is 'LED7S3', location is LC021, type is output.
 LED7S3  = LCELL( _EQ007 $  _EQ008);
  _EQ007 =  _LC031 &  _X001;
  _X001  = EXP(!A0 & !A1 & !A2 & !A3);
  _EQ008 = !A0 & !A1 & !A2 & !A3;

-- Node name is 'LED7S4' 
-- Equation name is 'LED7S4', location is LC019, type is output.
 LED7S4  = LCELL( _EQ009 $  _EQ010);
  _EQ009 =  _LC001 &  _X001;
  _X001  = EXP(!A0 & !A1 & !A2 & !A3);
  _EQ010 = !A0 & !A1 & !A2 & !A3;

-- Node name is 'LED7S5' 
-- Equation name is 'LED7S5', location is LC018, type is output.
 LED7S5  = LCELL( _EQ011 $  _EQ012);
  _EQ011 =  _LC005 &  _X001 &  _X002;
  _X001  = EXP(!A0 & !A1 & !A2 & !A3);
  _X002  = EXP( A0 & !A1 & !A2 & !A3);
  _EQ012 = !A0 & !A1 & !A2 & !A3;

-- Node name is 'LED7S6' 
-- Equation name is 'LED7S6', location is LC017, type is output.
 LED7S6  = LCELL( _EQ013 $  GND);
  _EQ013 =  _LC025 &  _X001 &  _X002;
  _X001  = EXP(!A0 & !A1 & !A2 & !A3);
  _X002  = EXP( A0 & !A1 & !A2 & !A3);

-- Node name is '~326~1' 
-- Equation name is '~326~1', location is LC025, type is buried.
-- synthesized logic cell 
_LC025   = LCELL( _EQ014 $  VCC);
  _EQ014 =  A0 &  A1 &  A2 & !A3
         # !A1 & !A2 & !A3 & !_LC024
         #  A2 &  A3 & !_LC024
         #  A1 &  A3 & !_LC024;

-- Node name is '~350~1' 
-- Equation name is '~350~1', location is LC024, type is buried.
-- synthesized logic cell 
_LC024   = LCELL( _EQ015 $  _EQ016);
  _EQ015 =  A0 & !A1 & !A2 & !A3 &  _X001
         # !_LC025 &  _X001;
  _X001  = EXP(!A0 & !A1 & !A2 & !A3);
  _EQ016 =  _X001;
  _X001  = EXP(!A0 & !A1 & !A2 & !A3);

-- Node name is '~377~1' 
-- Equation name is '~377~1', location is LC005, type is buried.
-- synthesized logic cell 
_LC005   = LCELL( _EQ017 $ !A1);
  _EQ017 = !A0 &  A1 &  A2 & !A3
         # !A1 &  A2 &  A3 & !_LC023
         # !A1 & !A2 & !A3 & !_LC023
         #  A1 &  A3 &  _LC023;

-- Node name is '~383~1' 
-- Equation name is '~383~1', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL( _EQ018 $  _EQ019);
  _EQ018 =  _LC005 &  _X001 &  _X002;
  _X001  = EXP(!A0 & !A1 & !A2 & !A3);
  _X002  = EXP( A0 & !A1 & !A2 & !A3);
  _EQ019 = !A0 & !A1 & !A2 & !A3;

-- Node name is '~413~1' 
-- Equation name is '~413~1', location is LC001, type is buried.
-- synthesized logic cell 
_LC001   = LCELL( _EQ020 $  GND);
  _EQ020 = !A0 & !A1 & !A2 &  A3 &  _X002
         # !A1 & !A2 & !A3 &  _LC032 &  _X002
         #  A2 &  A3 &  _LC032 &  _X002
         #  A1 &  A3 &  _LC032 &  _X002
         # !A0 &  A1 & !A3 &  _X002;
  _X002  = EXP( A0 & !A1 & !A2 & !A3);

-- Node name is '~416~1' 
-- Equation name is '~416~1', location is LC032, type is buried.
-- synthesized logic cell 
_LC032   = LCELL( _EQ021 $  VCC);
  _EQ021 = !_LC001 &  _X001;
  _X001  = EXP(!A0 & !A1 & !A2 & !A3);

-- Node name is '~446~1' 
-- Equation name is '~446~1', location is LC031, type is buried.
-- synthesized logic cell 
_LC031   = LCELL( _EQ022 $  _EQ023);
  _EQ022 =  A0 &  A1 &  A2 & !A3 &  _X002
         # !A0 & !A1 &  A2 & !A3 &  _X002
         # !A1 & !A2 & !A3 & !_LC030 &  _X002
         #  A3 & !_LC030 &  _X002 &  _X003;
  _X002  = EXP( A0 & !A1 & !A2 & !A3);
  _X003  = EXP(!A1 & !A2);
  _EQ023 =  _X002;
  _X002  = EXP( A0 & !A1 & !A2 & !A3);

-- Node name is '~449~1' 
-- Equation name is '~449~1', location is LC030, type is buried.
-- synthesized logic cell 
_LC030   = LCELL( _EQ024 $  VCC);
  _EQ024 = !_LC031 &  _X001;
  _X001  = EXP(!A0 & !A1 & !A2 & !A3);

-- Node name is '~479~1' 
-- Equation name is '~479~1', location is LC012, type is buried.
-- synthesized logic cell 
_LC012   = LCELL( _EQ025 $  VCC);
  _EQ025 = !A0 &  A1 & !A2 & !A3 &  _X002
         # !A1 & !A2 & !A3 & !_LC020 &  _X002
         #  A2 &  A3 & !_LC020 &  _X002
         #  A1 &  A3 & !_LC020 &  _X002;
  _X002  = EXP( A0 & !A1 & !A2 & !A3);

-- Node name is '~482~1' 
-- Equation name is '~482~1', location is LC020, type is buried.
-- synthesized logic cell 
_LC020   = LCELL( _EQ026 $  VCC);
  _EQ026 = !_LC012 &  _X001;
  _X001  = EXP(!A0 & !A1 & !A2 & !A3);

-- Node name is '~512~1' 
-- Equation name is '~512~1', location is LC004, type is buried.
-- synthesized logic cell 
_LC004   = LCELL( _EQ027 $  VCC);
  _EQ027 =  A0 & !A1 &  A2 & !A3 &  _X002
         # !A0 &  A1 &  A2 & !A3 &  _X002
         # !A1 & !A2 & !A3 & !_LC022 &  _X002
         #  A2 &  A3 & !_LC022 &  _X002
         #  A1 &  A3 & !_LC022 &  _X002;
  _X002  = EXP( A0 & !A1 & !A2 & !A3);

-- Node name is '~515~1' 
-- Equation name is '~515~1', location is LC022, type is buried.
-- synthesized logic cell 
_LC022   = LCELL( _EQ028 $  VCC);
  _EQ028 = !_LC004 &  _X001;
  _X001  = EXP(!A0 & !A1 & !A2 & !A3);

-- Node name is '~545~1' 
-- Equation name is '~545~1', location is LC008, type is buried.
-- synthesized logic cell 
_LC008   = LCELL( _EQ029 $  _EQ030);
  _EQ029 = !A0 & !A1 &  A2 & !A3 &  _X002
         # !A1 & !A2 & !A3 & !_LC027 &  _X002
         #  A2 &  A3 & !_LC027 &  _X002
         #  A1 &  A3 & !_LC027 &  _X002;
  _X002  = EXP( A0 & !A1 & !A2 & !A3);
  _EQ030 =  _X002;
  _X002  = EXP( A0 & !A1 & !A2 & !A3);

-- Node name is '~548~1' 
-- Equation name is '~548~1', location is LC027, type is buried.
-- synthesized logic cell 
_LC027   = LCELL( _EQ031 $  VCC);
  _EQ031 = !_LC008 &  _X001;
  _X001  = EXP(!A0 & !A1 & !A2 & !A3);



--     Shareable expanders that are duplicated in multiple LABs:
--    _X002 occurs in LABs A, B




Project Information                e:\eda_all\quartusii_eda(hust)\1\decl7s.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,549K