📄 decl7s.rpt
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Project Information e:\eda_all\quartusii_eda(hust)\1\decl7s.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 05/14/2009 11:55:49
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
DECL7S
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
decl7s EPM7032SLC44-5 4 7 0 21 4 65 %
User Pins: 4 7 0
Device-Specific Information: e:\eda_all\quartusii_eda(hust)\1\decl7s.rpt
decl7s
***** Logic for device 'decl7s' compiled without errors.
Device: EPM7032SLC44-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
L L
E E
D D
V G G G G G 7 7
A A A C N N N N N S S
2 1 0 C D D D D D 6 5
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
#TDI | 7 39 | LED7S4
A3 | 8 38 | #TDO
RESERVED | 9 37 | LED7S3
GND | 10 36 | RESERVED
RESERVED | 11 35 | VCC
RESERVED | 12 EPM7032SLC44-5 34 | RESERVED
#TMS | 13 33 | RESERVED
RESERVED | 14 32 | #TCK
VCC | 15 31 | LED7S0
RESERVED | 16 30 | GND
RESERVED | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R R L L
E E E E N C E E E E E
S S S S D C S S S D D
E E E E E E E 7 7
R R R R R R R S S
V V V V V V V 2 1
E E E E E E E
D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\eda_all\quartusii_eda(hust)\1\decl7s.rpt
decl7s
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 5/16( 31%) 6/16( 37%) 5/16( 31%) 9/36( 25%)
B: LC17 - LC32 16/16(100%) 9/16( 56%) 4/16( 25%) 13/36( 36%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 15/32 ( 46%)
Total logic cells used: 21/32 ( 65%)
Total shareable expanders used: 4/32 ( 12%)
Total Turbo logic cells used: 21/32 ( 65%)
Total shareable expanders not available (n/a): 5/32 ( 15%)
Average fan-in: 5.00
Total fan-in: 105
Total input pins required: 4
Total fast input logic cells required: 0
Total output pins required: 7
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 21
Total flipflops required: 0
Total product terms required: 60
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 3
Synthesized logic cells: 14/ 32 ( 43%)
Device-Specific Information: e:\eda_all\quartusii_eda(hust)\1\decl7s.rpt
decl7s
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 7 14 A0
5 (2) (A) INPUT 0 0 0 0 0 7 14 A1
6 (3) (A) INPUT 0 0 0 0 0 7 14 A2
8 (5) (A) INPUT 0 0 0 0 0 7 14 A3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\eda_all\quartusii_eda(hust)\1\decl7s.rpt
decl7s
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
31 26 B OUTPUT t 1 1 0 4 1 0 0 LED7S0
28 28 B OUTPUT t 1 1 0 4 1 0 0 LED7S1
27 29 B OUTPUT t 1 1 0 4 1 0 0 LED7S2
37 21 B OUTPUT t 1 1 0 4 1 0 0 LED7S3
39 19 B OUTPUT t 1 1 0 4 1 0 0 LED7S4
40 18 B OUTPUT t 2 2 0 4 1 0 0 LED7S5
41 17 B OUTPUT t 2 2 0 4 1 0 0 LED7S6
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\eda_all\quartusii_eda(hust)\1\decl7s.rpt
decl7s
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(32) 25 B SOFT s t 0 0 0 4 1 1 1 ~326~1
(33) 24 B LCELL s t 1 1 0 4 1 0 1 ~350~1
(8) 5 A SOFT s t 1 0 1 4 1 1 1 ~377~1
(34) 23 B LCELL s t 2 2 0 4 1 0 1 ~383~1
(4) 1 A SOFT s t 2 1 1 4 1 1 1 ~413~1
(24) 32 B LCELL s t 1 1 0 4 1 0 1 ~416~1
(25) 31 B SOFT s t 3 1 1 4 1 1 1 ~446~1
(26) 30 B LCELL s t 1 1 0 4 1 0 1 ~449~1
(17) 12 A SOFT s t 1 1 0 4 1 1 1 ~479~1
(38) 20 B LCELL s t 1 1 0 4 1 0 1 ~482~1
(7) 4 A SOFT s t 2 1 1 4 1 1 1 ~512~1
(36) 22 B LCELL s t 1 1 0 4 1 0 1 ~515~1
(12) 8 A SOFT s t 2 1 1 4 1 1 1 ~545~1
(29) 27 B LCELL s t 1 1 0 4 1 0 1 ~548~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\eda_all\quartusii_eda(hust)\1\decl7s.rpt
decl7s
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------- LC5 ~377~1
| +------- LC1 ~413~1
| | +----- LC12 ~479~1
| | | +--- LC4 ~512~1
| | | | +- LC8 ~545~1
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'A'
LC | | | | | | A B | Logic cells that feed LAB 'A':
Pin
4 -> * * * * * | * * | <-- A0
5 -> * * * * * | * * | <-- A1
6 -> * * * * * | * * | <-- A2
8 -> * * * * * | * * | <-- A3
LC23 -> * - - - - | * - | <-- ~383~1
LC32 -> - * - - - | * - | <-- ~416~1
LC20 -> - - * - - | * - | <-- ~482~1
LC22 -> - - - * - | * - | <-- ~515~1
LC27 -> - - - - * | * - | <-- ~548~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\eda_all\quartusii_eda(hust)\1\decl7s.rpt
decl7s
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC26 LED7S0
| +----------------------------- LC28 LED7S1
| | +--------------------------- LC29 LED7S2
| | | +------------------------- LC21 LED7S3
| | | | +----------------------- LC19 LED7S4
| | | | | +--------------------- LC18 LED7S5
| | | | | | +------------------- LC17 LED7S6
| | | | | | | +----------------- LC25 ~326~1
| | | | | | | | +--------------- LC24 ~350~1
| | | | | | | | | +------------- LC23 ~383~1
| | | | | | | | | | +----------- LC32 ~416~1
| | | | | | | | | | | +--------- LC31 ~446~1
| | | | | | | | | | | | +------- LC30 ~449~1
| | | | | | | | | | | | | +----- LC20 ~482~1
| | | | | | | | | | | | | | +--- LC22 ~515~1
| | | | | | | | | | | | | | | +- LC27 ~548~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC25 -> - - - - - - * - * - - - - - - - | - * | <-- ~326~1
LC24 -> - - - - - - - * - - - - - - - - | - * | <-- ~350~1
LC31 -> - - - * - - - - - - - - * - - - | - * | <-- ~446~1
LC30 -> - - - - - - - - - - - * - - - - | - * | <-- ~449~1
Pin
4 -> * * * * * * * * * * * * * * * * | * * | <-- A0
5 -> * * * * * * * * * * * * * * * * | * * | <-- A1
6 -> * * * * * * * * * * * * * * * * | * * | <-- A2
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