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Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "clk_contrl.v"Module <clk_contrl> compiledCompiling verilog file "front.v"Module <front> compiledCompiling verilog file "a_task.v"ERROR:HDLCompilers:28 - "a_task.v" line 31 'rst' has not been declaredERROR:HDLCompilers:28 - "a_task.v" line 31 'clk_2_5' has not been declaredERROR:HDLCompilers:28 - "a_task.v" line 33 'rst' has not been declaredERROR:HDLCompilers:28 - "a_task.v" line 35 'rdy' has not been declaredERROR:HDLCompilers:28 - "a_task.v" line 40 'indata' has not been declaredModule <a_task> compiledCompiling verilog file "b_task.v"Module <b_task> compiledCompiling verilog file "back.v"Module <back> compiledCompiling verilog file "pingpang.v"Module <pingpang> compiledAnalysis of file <"pingpang.prj"> failed.--> Total memory usage is 77136 kilobytesNumber of errors   :    5 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "clk_contrl.v"Module <clk_contrl> compiledCompiling verilog file "front.v"Module <front> compiledCompiling verilog file "a_task.v"ERROR:HDLCompilers:28 - "a_task.v" line 31 'rst' has not been declaredERROR:HDLCompilers:28 - "a_task.v" line 31 'clk_2_5' has not been declaredERROR:HDLCompilers:28 - "a_task.v" line 33 'rst' has not been declaredERROR:HDLCompilers:28 - "a_task.v" line 40 'indata' has not been declaredModule <a_task> compiledCompiling verilog file "b_task.v"Module <b_task> compiledCompiling verilog file "back.v"Module <back> compiledCompiling verilog file "pingpang.v"Module <pingpang> compiledAnalysis of file <"pingpang.prj"> failed.--> Total memory usage is 77136 kilobytesNumber of errors   :    4 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "clk_contrl.v"Module <clk_contrl> compiledCompiling verilog file "front.v"Module <front> compiledCompiling verilog file "a_task.v"ERROR:HDLCompilers:28 - "a_task.v" line 32 'clk_2_5' has not been declaredERROR:HDLCompilers:28 - "a_task.v" line 41 'indata' has not been declaredModule <a_task> compiledCompiling verilog file "b_task.v"Module <b_task> compiledCompiling verilog file "back.v"Module <back> compiledCompiling verilog file "pingpang.v"Module <pingpang> compiledAnalysis of file <"pingpang.prj"> failed.--> Total memory usage is 77136 kilobytesNumber of errors   :    2 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "clk_contrl.v"Module <clk_contrl> compiledCompiling verilog file "front.v"Module <front> compiledCompiling verilog file "a_task.v"ERROR:HDLCompilers:28 - "a_task.v" line 41 'indata' has not been declaredModule <a_task> compiledCompiling verilog file "b_task.v"Module <b_task> compiledCompiling verilog file "back.v"Module <back> compiledCompiling verilog file "pingpang.v"Module <pingpang> compiledAnalysis of file <"pingpang.prj"> failed.--> Total memory usage is 77136 kilobytesNumber of errors   :    1 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "clk_contrl.v"Module <clk_contrl> compiledCompiling verilog file "front.v"Module <front> compiledCompiling verilog file "a_task.v"Module <a_task> compiledCompiling verilog file "b_task.v"Module <b_task> compiledCompiling verilog file "back.v"Module <back> compiledCompiling verilog file "pingpang.v"Module <pingpang> compiledNo errors in compilationAnalysis of file <"pingpang.prj"> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================WARNING:HDLCompilers:93 - "pingpang.v" line 31 Too few port connections in instance 'a_task_1' of module 'a_task'WARNING:HDLCompilers:261 - "pingpang.v" line 30 Connection to output port 'a' does not match port sizeWARNING:HDLCompilers:261 - "pingpang.v" line 30 Connection to output port 'b' does not match port sizeWARNING:HDLCompilers:259 - "pingpang.v" line 31 Connection to input port 'indata_a' does not match port sizeWARNING:HDLCompilers:261 - "pingpang.v" line 31 Connection to output port 'out_a' does not match port sizeWARNING:HDLCompilers:259 - "pingpang.v" line 32 Connection to input port 'indata_b' does not match port sizeWARNING:HDLCompilers:261 - "pingpang.v" line 32 Connection to output port 'out_b' does not match port sizeWARNING:HDLCompilers:259 - "pingpang.v" line 33 Connection to input port 'indata_a' does not match port sizeWARNING:HDLCompilers:259 - "pingpang.v" line 33 Connection to input port 'indata_b' does not match port sizeWARNING:HDLCompilers:259 - "pingpang.v" line 33 Connection to input port 'out' does not match port sizeAnalyzing top module <pingpang>.Module <pingpang> is correct for synthesis. Analyzing module <clk_contrl>.Module <clk_contrl> is correct for synthesis. Analyzing module <front>.Module <front> is correct for synthesis. Analyzing module <a_task>.ERROR:Xst:899 - "a_task.v" line 44: The logic for <rdy_a> does not match a known FF or Latch template. Found 1 error(s). Aborting synthesis.--> Total memory usage is 77136 kilobytesNumber of errors   :    1 (   0 filtered)Number of warnings :   10 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "clk_contrl.v"Module <clk_contrl> compiledCompiling verilog file "front.v"Module <front> compiledCompiling verilog file "a_task.v"Module <a_task> compiledCompiling verilog file "b_task.v"Module <b_task> compiledCompiling verilog file "back.v"Module <back> compiledCompiling verilog file "pingpang.v"Module <pingpang> compiledNo errors in compilationAnalysis of file <"pingpang.prj"> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================WARNING:HDLCompilers:93 - "pingpang.v" line 31 Too few port connections in instance 'a_task_1' of module 'a_task'WARNING:HDLCompilers:261 - "pingpang.v" line 30 Connection to output port 'a' does not match port sizeWARNING:HDLCompilers:261 - "pingpang.v" line 30 Connection to output port 'b' does not match port sizeWARNING:HDLCompilers:259 - "pingpang.v" line 31 Connection to input port 'indata_a' does not match port sizeWARNING:HDLCompilers:261 - "pingpang.v" line 31 Connection to output port 'out_a' does not match port sizeWARNING:HDLCompilers:259 - "pingpang.v" line 32 Connection to input port 'indata_b' does not match port sizeWARNING:HDLCompilers:261 - "pingpang.v" line 32 Connection to output port 'out_b' does not match port sizeWARNING:HDLCompilers:259 - "pingpang.v" line 33 Connection to input port 'indata_a' does not match port sizeWARNING:HDLCompilers:259 - "pingpang.v" line 33 Connection to input port 'indata_b' does not match port sizeWARNING:HDLCompilers:259 - "pingpang.v" line 33 Connection to input port 'out' does not match port sizeAnalyzing top module <pingpang>.Module <pingpang> is correct for synthesis. Analyzing module <clk_contrl>.Module <clk_contrl> is correct for synthesis. Analyzing module <front>.Module <front> is correct for synthesis. Analyzing module <a_task>.ERROR:Xst:899 - "a_task.v" line 44: The logic for <rdy_a> does not match a known FF or Latch template. Found 1 error(s). Aborting synthesis.--> Total memory usage is 77136 kilobytesNumber of errors   :    1 (   0 filtered)Number of warnings :   10 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling verilog file "clk_contrl.v"Module <clk_contrl> compiledCompiling verilog file "front.v"Module <front> compiledCompiling verilog file "a_task.v"Module <a_task> compiledCompiling verilog file "b_task.v"Module <b_task> compiledCompiling verilog file "back.v"Module <back> compiledCompiling verilog file "pingpang.v"Module <pingpang> compiledNo errors in compilationAnalysis of file <"pingpang.prj"> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================WARNING:HDLCompilers:93 - "pingpang.v" line 31 Too few port connections in instance 'a_task_1' of module 'a_task'WARNING:HDLCompilers:261 - "pingpang.v" line 30 Connection to output port 'a' does not match port sizeWARNING:HDLCompilers:261 - "pingpang.v" line 30 Connection to output port 'b' does not match port sizeWARNING:HDLCompilers:259 - "pingpang.v" line 31 Connection to input port 'indata_a' does not match port sizeWARNING:HDLCompilers:261 - "pingpang.v" line 31 Connection to output port 'out_a' does not match port size
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