pingpang.syr

关于乒乓操作的

RTL Top Level Output File Name     : pingpang.ngr
Top Level Output File Name         : pingpang
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 36

Macro Statistics :
# Registers                        : 14
#      1-bit register              : 9
#      16-bit register             : 5

Cell Usage :
# BELS                             : 94
#      INV                         : 35
#      LUT2                        : 5
#      LUT3                        : 4
#      LUT3_L                      : 33
#      LUT4_L                      : 1
#      MUXF5                       : 16
# FlipFlops/Latches                : 89
#      FDC                         : 6
#      FDCE                        : 2
#      FDE                         : 80
#      FDP                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 35
#      IBUF                        : 18
#      OBUF                        : 17
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                      58  out of   3584     1%  
 Number of Slice Flip Flops:            89  out of   7168     1%  
 Number of 4 input LUTs:                43  out of   7168     0%  
 Number of bonded IOBs:                 36  out of    141    25%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_5m                             | BUFGP                  | 55    |
clk_contrl_1/clk_2_5m:Q            | NONE                   | 17    |
clk_contrl_1/clk_2_5m_inv:Q        | NONE                   | 17    |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 4.319ns (Maximum Frequency: 231.535MHz)
   Minimum input arrival time before clock: 4.593ns
   Maximum output required time after clock: 7.271ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk_5m'
  Clock period: 4.099ns (frequency: 243.962MHz)
  Total number of paths / destination ports: 90 / 55
-------------------------------------------------------------------------
Delay:               4.099ns (Levels of Logic = 1)
  Source:            front_1/state (FF)
  Destination:       front_1/a_12 (FF)
  Source Clock:      clk_5m rising
  Destination Clock: clk_5m rising

  Data Path: front_1/state to front_1/a_12
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              5   0.720   0.989  front_1/state (front_1/state)
     LUT3:I2->O           16   0.551   1.237  front_1/_n00041 (front_1/_n0004)
     FDE:CE                    0.602          front_1/b_0
    ----------------------------------------
    Total                      4.099ns (1.873ns logic, 2.226ns route)
                                       (45.7% logic, 54.3% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk_contrl_1/clk_2_5m:Q'
  Clock period: 4.319ns (frequency: 231.535MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               4.319ns (Levels of Logic = 1)
  Source:            a_task_1/rdy_a (FF)
  Destination:       a_task_1/rdy_a (FF)
  Source Clock:      clk_contrl_1/clk_2_5m:Q rising
  Destination Clock: clk_contrl_1/clk_2_5m:Q rising

  Data Path: a_task_1/rdy_a to a_task_1/rdy_a
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            19   0.720   1.645  a_task_1/rdy_a (a_task_1/rdy_a)
     LUT2:I1->O            1   0.551   0.801  a_task_1/_n00051 (a_task_1/_n0005)
     FDCE:CE                   0.602          a_task_1/rdy_a
    ----------------------------------------
    Total                      4.319ns (1.873ns logic, 2.446ns route)
                                       (43.4% logic, 56.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk_contrl_1/clk_2_5m_inv:Q'
  Clock period: 4.319ns (frequency: 231.535MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               4.319ns (Levels of Logic = 1)
  Source:            b_task_1/rdy_b (FF)
  Destination:       b_task_1/rdy_b (FF)
  Source Clock:      clk_contrl_1/clk_2_5m_inv:Q rising
  Destination Clock: clk_contrl_1/clk_2_5m_inv:Q rising

  Data Path: b_task_1/rdy_b to b_task_1/rdy_b
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            19   0.720   1.645  b_task_1/rdy_b (b_task_1/rdy_b)
     LUT2:I1->O            1   0.551   0.801  b_task_1/_n00051 (b_task_1/_n0005)
     FDCE:CE                   0.602          b_task_1/rdy_b
    ----------------------------------------
    Total                      4.319ns (1.873ns logic, 2.446ns route)
                                       (43.4% logic, 56.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_5m'
  Total number of paths / destination ports: 115 / 83
-------------------------------------------------------------------------
Offset:              4.593ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       front_1/a_12 (FF)
  Destination Clock: clk_5m rising

  Data Path: rst to front_1/a_12
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            14   0.821   1.382  rst_IBUF (rst_IBUF)
     LUT3:I1->O           16   0.551   1.237  front_1/_n00031 (front_1/_n0003)
     FDE:CE                    0.602          front_1/a_0
    ----------------------------------------
    Total                      4.593ns (1.974ns logic, 2.619ns route)
                                       (43.0% logic, 57.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_contrl_1/clk_2_5m:Q'
  Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------
Offset:              4.593ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       a_task_1/out_a_13 (FF)
  Destination Clock: clk_contrl_1/clk_2_5m:Q rising

  Data Path: rst to a_task_1/out_a_13
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            14   0.821   1.382  rst_IBUF (rst_IBUF)
     LUT2:I1->O           16   0.551   1.237  a_task_1/_n00021 (a_task_1/_n0002)
     FDE:CE                    0.602          a_task_1/out_a_0
    ----------------------------------------
    Total                      4.593ns (1.974ns logic, 2.619ns route)
                                       (43.0% logic, 57.0% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_contrl_1/clk_2_5m_inv:Q'
  Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------
Offset:              4.593ns (Levels of Logic = 2)
  Source:            rst (PAD)
  Destination:       b_task_1/out_b_13 (FF)
  Destination Clock: clk_contrl_1/clk_2_5m_inv:Q rising

  Data Path: rst to b_task_1/out_b_13
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            14   0.821   1.382  rst_IBUF (rst_IBUF)
     LUT2:I1->O           16   0.551   1.237  b_task_1/_n00021 (b_task_1/_n0002)
     FDE:CE                    0.602          b_task_1/out_b_0
    ----------------------------------------
    Total                      4.593ns (1.974ns logic, 2.619ns route)
                                       (43.0% logic, 57.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_5m'
  Total number of paths / destination ports: 17 / 17
-------------------------------------------------------------------------
Offset:              7.271ns (Levels of Logic = 1)
  Source:            back_1/out_15 (FF)
  Destination:       out<15> (PAD)
  Source Clock:      clk_5m rising

  Data Path: back_1/out_15 to out<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              3   0.720   0.907  back_1/out_15 (back_1/out_15)
     OBUF:I->O                 5.644          out_15_OBUF (out<15>)
    ----------------------------------------
    Total                      7.271ns (6.364ns logic, 0.907ns route)
                                       (87.5% logic, 12.5% route)

=========================================================================
CPU : 4.66 / 5.08 s | Elapsed : 5.00 / 5.00 s
 
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Total memory usage is 101824 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    1 (   0 filtered)