📄 lwbbuschange.v
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///////////////////////////////////////////////////////////////////////// //////// LWB rev 1.2 -- BUS CHANGE FOR TWO SRAMS //////// //////// //////// Author: Liu Tao //////// liutao94@tsinghua.org.cn //////// //////// //////// ///////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2003 Liu Tao //////// liutao94@tsinghua.org.cn //////// //////// /////////////////////////////////////////////////////////////////////////`timescale 1ns / 10psmodule LWBBUSCHANGE (EA_SRAM,CE_SRAM,OE_SRAM,WE_SRAM,ld,la,SRAM_CE_,SRAM_OE_,SRAM_WE_,SRAM_1_IN_ED,SRAM_2_IN_ED,toggle,ED_SRAM,SRAM_1_CE_,SRAM_1_OE_,SRAM_1_WE_,SRAM_1_EA,SRAM_1_O_ED,SRAM_1_OEN,SRAM_2_CE_,SRAM_2_OE_,SRAM_2_WE_,SRAM_2_EA,SRAM_2_O_ED,SRAM_2_OEN); //================================================================================= //input //================================================================================= /*___________________________________________________ */ //from C6711 EMIF interface,DECODE input [18:0] EA_SRAM; input CE_SRAM; input OE_SRAM; input WE_SRAM; /*___________________________________________________ */ //from SAA7113 interface input [7:0] ld;//data bus,to sram input [18:0] la;//address bus,to sram input SRAM_CE_; input SRAM_OE_; input SRAM_WE_; /*___________________________________________________ */ //from SRAM1 input [7:0] SRAM_1_IN_ED; /*___________________________________________________ */ //FROM SRAM2 input [7:0] SRAM_2_IN_ED; /*___________________________________________________ */ //from top logic control,toggle flag input toggle; //================================================================================= //output //================================================================================= /*___________________________________________________ */ //TO C6711 EMIF interface output [7:0] ED_SRAM; /*___________________________________________________ */ //to SRAM1 output SRAM_1_CE_;//ce output SRAM_1_OE_;//oe output SRAM_1_WE_;//we output [18:0] SRAM_1_EA;//address bus output [7:0] SRAM_1_O_ED;//data bus output to sram output SRAM_1_OEN;//data output enable /*___________________________________________________ */ //to SRAM1 output SRAM_2_CE_;//ce output SRAM_2_OE_;//oe output SRAM_2_WE_;//we output [18:0] SRAM_2_EA;//address bus output [7:0] SRAM_2_O_ED;//data bus output to sram output SRAM_2_OEN;//data output enable //================================================================================= //assinging //================================================================================= //toggle =1 ,dsp EMIF interface connect to sram1,dsp read data from sram1 assign ED_SRAM = toggle ? SRAM_1_IN_ED : SRAM_2_IN_ED; assign SRAM_1_O_ED = toggle ? 8'hzz : ld; assign SRAM_1_OEN = toggle ? 1'b0 : 1'b1; assign SRAM_1_EA = toggle ? EA_SRAM : la; assign SRAM_1_CE_ = toggle ? CE_SRAM : SRAM_CE_;//toggle =1 ,output dsp to sram1;0,output saa7113 to sram1 assign SRAM_1_OE_ = toggle ? OE_SRAM : SRAM_OE_; assign SRAM_1_WE_ = toggle ? WE_SRAM : SRAM_WE_; //toggle =1 ,saa7113 interface connect to sram2,saa7113 write data to sram2 assign SRAM_2_O_ED = toggle ? ld : 8'hzz; assign SRAM_2_OEN = toggle ? 1'b1 : 1'b0; assign SRAM_2_EA = toggle ? la : EA_SRAM; assign SRAM_2_CE_ = toggle ? SRAM_CE_: CE_SRAM ;//toggle =1 ,output SAA7113 to sram1;0,output DSP to sram1 assign SRAM_2_OE_ = toggle ? SRAM_OE_: OE_SRAM ; assign SRAM_2_WE_ = toggle ? SRAM_WE_: WE_SRAM ;endmodule
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