tst_saa7113.v

saa7113配置

module tst_saa7113 (error,dsprst,xreset,saareset,ARDY,ED_O,ED_OEN_O,SRAM_1_EA,SRAM_2_EA,SRAM_1_O_ED,SRAM_2_O_ED);

	//REGS
	reg reset;
	reg clk;//50MHz
	reg llck;//here is 25MHz,in fact it is 27MHz
	reg [7:0] vpo;//image data and other data from saa7113
	reg capture;//flag to indicate capture image data
	reg toggle;//flag to indicate change bus
	reg [1:0] rst;

	//input
	input error;
	input dsprst,xreset,saareset;
	input ARDY;
	input [7:0] ED_O;
	input ED_OEN_O;


	input [18:0] SRAM_1_EA;
	input [7:0] SRAM_1_O_ED;
	input [18:0] SRAM_2_EA;
	input [7:0] SRAM_2_O_ED;

	//from dsp
	reg CE3_;
	reg ARE_;
	reg AWE_;
	reg [21:2] EA;
	reg [7:0] ED_I;

	//TO DSP
//	reg ARDY;
//	reg [7:0] ED_O;
//	reg ED_OEN_O;


	//TO SRAM
	reg [7:0] SRAM_1_IN_ED;
	reg [7:0] SRAM_2_IN_ED;
//	reg [18:0] SRAM_1_EA;
//	reg [7:0] SRAM_1_O_ED;
//	reg [18:0] SRAM_2_EA;
//	reg [7:0] SRAM_2_O_ED;

	//wires
	//from saa7113
	wire SRAM_CE_;
	wire SRAM_OE_;
	wire SRAM_WE_;
	wire [18:0] la;
	wire [7:0] ld;

	//FROM DSP
	wire CE_SRAM;
	wire WE_SRAM;
	wire OE_SRAM;
	wire [7:0] ED_SRAM;
	wire [18:0] EA_SRAM;





	//hookup
	LWBSAA7113 L_SAA7113 (
		.reset(reset),
		.clk(clk),
		.llck(llck),
		.vpo(vpo),
		.rst(rst),
		.capture(capture),
		.error(error),
		.SRAM_CE_(SRAM_CE_),
		.SRAM_OE_(SRAM_OE_),
		.SRAM_WE_(SRAM_WE_),
		.la(la),
		.ld(ld)
	);




	LWBDECODE L_DECODE (
		.reset(reset),
		.CE3_(CE3_),
		.ARE_(ARE_),
		.AWE_(AWE_),
		.EA(EA),
		.ED_I(ED_I),
		.ED_O(ED_O),
		.ED_OEN_O(ED_OEN_O),
		.ARDY(ARDY),
		.EA_SRAM(EA_SRAM),
		.ED_SRAM(ED_SRAM),
		.CE_SRAM(CE_SRAM),
		.WE_SRAM(WE_SRAM),
		.OE_SRAM(OE_SRAM),
		.dsprst(dsprst),
		.xreset(xreset),
		.saareset(saareset)
	);


//SRAM_1_CE_,SRAM_1_OE_,SRAM_1_WE_,SRAM_1_EA,SRAM_1_O_ED,SRAM_1_OEN,SRAM_2_CE_,SRAM_2_OE_,SRAM_2_WE_,SRAM_2_EA,SRAM_2_O_ED,SRAM_2_OEN

	LWBBUSCHANGE L_BUSCHANGE (
		.EA_SRAM(EA_SRAM),
		.ED_SRAM(ED_SRAM),
		.CE_SRAM(CE_SRAM),
		.WE_SRAM(WE_SRAM),
		.OE_SRAM(OE_SRAM),
		.la(la),
		.ld(ld),
		.SRAM_CE_(SRAM_CE_),
		.SRAM_WE_(SRAM_WE_),
		.SRAM_OE_(SRAM_OE_),
		.SRAM_1_IN_ED(SRAM_1_IN_ED),
		.SRAM_2_IN_ED(SRAM_2_IN_ED),
		.toggle(toggle),
		.SRAM_1_EA(SRAM_1_EA),
		.SRAM_1_O_ED(SRAM_1_O_ED),
		.SRAM_2_EA(SRAM_2_EA),
		.SRAM_2_O_ED(SRAM_2_O_ED)
	);
		
	//clock
	always #10 clk=~clk;
	always #20 llck = ~llck;


	initial
		begin
		    #2;
			$display("\n status : %t TestBench of saa7113 started! \n\n",$time);

			//initial value
			clk = 0;
			#7;
			llck =0;

			//reset
			reset = 1;
	
			//dsp initial
			ARE_ = 1;
			AWE_ = 1;
			CE3_ = 1;
			
			//capture and toggle
			capture = 0;
			toggle = 1;

			#2;
			reset = 0;
			
		 	repeat(20) @(posedge clk);
			reset = 1'b1; // negate reset

			//dsp read data
			SRAM_1_IN_ED = 8'h1d;
			SRAM_2_IN_ED = 8'h2d;


			//dsp address bus
			EA[21:16] = 6'b000000;
			EA[15:7] = 9'b000000000;
			EA[6:2]= 5'b00001;

			#5;
			CE3_ = 0;						
			ARE_ = 0;


			//saa7113 write data
			capture = 1;
			#5;
			@(posedge llck) vpo = 8'haa;
			@(posedge llck) vpo = 8'hbb;
			@(posedge llck) vpo = 8'hcc;
			@(posedge llck) vpo = 8'hdd;
			@(posedge llck) vpo = 8'hee;

			//vertical blanking stage
			//1
			@(posedge llck) vpo = 8'hff;//begin
			@(posedge llck) vpo = 8'h00;
			@(posedge llck) vpo = 8'h00;
			@(posedge llck) vpo = 8'b00100000;//sav

			//2
			@(posedge llck) vpo = 8'hff;//begin
			@(posedge llck) vpo = 8'h00;
			@(posedge llck) vpo = 8'h00;
			@(posedge llck) vpo = 8'b00100000;

			//data start
			@(posedge llck) vpo = 8'hff;//begin
			@(posedge llck) vpo = 8'h00;
			@(posedge llck) vpo = 8'h00;
			@(posedge llck) vpo = 8'b00000000;

			//data
			@(posedge llck) vpo = 8'h01;//Cb
			@(posedge llck) vpo = 8'h02;//Yb
			@(posedge llck) vpo = 8'h03;//Cr
			@(posedge llck) vpo = 8'h04;//Yr--1

			@(posedge llck) vpo = 8'h05;//Cb
			@(posedge llck) vpo = 8'h06;//Yb
			@(posedge llck) vpo = 8'h07;//Cr
			@(posedge llck) vpo = 8'h08;//Yr--2

			@(posedge llck) vpo = 8'h09;//Cb
			@(posedge llck) vpo = 8'h0a;//Yb
			@(posedge llck) vpo = 8'h0b;//Cr
			@(posedge llck) vpo = 8'h0c;//Yr--3

			@(posedge llck) vpo = 8'h0d;//Cb
			@(posedge llck) vpo = 8'h0e;//Yb
			@(posedge llck) vpo = 8'h0f;//Cr
			@(posedge llck) vpo = 8'h10;//Yr--4

			@(posedge llck) vpo = 8'h11;//Cb
			@(posedge llck) vpo = 8'h12;//Yb
			@(posedge llck) vpo = 8'h13;//Cr
			@(posedge llck) vpo = 8'h14;//Yr--5

			@(posedge llck) vpo = 8'h15;//Cb
			@(posedge llck) vpo = 8'h16;//Yb
			@(posedge llck) vpo = 8'h17;//Cr
			@(posedge llck) vpo = 8'h18;//Yr--6

			@(posedge llck) vpo = 8'h19;//Cb
			@(posedge llck) vpo = 8'h1a;//Yb
			@(posedge llck) vpo = 8'h1b;//Cr
			@(posedge llck) vpo = 8'h1c;//Yr--7

			@(posedge llck) vpo = 8'h1d;//Cb
			@(posedge llck) vpo = 8'h1e;//Yb
			@(posedge llck) vpo = 8'h1f;//Cr
			@(posedge llck) vpo = 8'h20;//Yr--8

			@(posedge llck) vpo = 8'h21;//Cb
			@(posedge llck) vpo = 8'h22;//Yb
			@(posedge llck) vpo = 8'h23;//Cr
			@(posedge llck) vpo = 8'h24;//Yr--9

			@(posedge llck) vpo = 8'h25;//Cb
			@(posedge llck) vpo = 8'h26;//Yb
			@(posedge llck) vpo = 8'h27;//Cr
			@(posedge llck) vpo = 8'h28;//Yr--10

			@(posedge llck) vpo = 8'h29;//Cb
			@(posedge llck) vpo = 8'h3a;//Yb
			@(posedge llck) vpo = 8'h3b;//Cr
			@(posedge llck) vpo = 8'h3c;//Yr--11


			//DATA END
			@(posedge llck) vpo = 8'hff;//ff
			@(posedge llck) vpo = 8'h00;//00
			@(posedge llck) vpo = 8'h00;//00
			@(posedge llck) vpo = 8'b01110000;//end of field 1

			#20;
			
			ARE_ = 1;			
			
			capture = 0;

			#200;
			
			
			toggle = 0;
			
			#100;
			
			ARE_ = 0;			
			
			capture = 1;

			//vertical blanking stage
			//1
			@(posedge llck) vpo = 8'hff;//begin
			@(posedge llck) vpo = 8'h00;
			@(posedge llck) vpo = 8'h00;
			@(posedge llck) vpo = 8'b00100000;//sav

			//2
			@(posedge llck) vpo = 8'hff;//begin
			@(posedge llck) vpo = 8'h00;
			@(posedge llck) vpo = 8'h00;
			@(posedge llck) vpo = 8'b00100000;

			//data start
			@(posedge llck) vpo = 8'hff;//begin
			@(posedge llck) vpo = 8'h00;
			@(posedge llck) vpo = 8'h00;
			@(posedge llck) vpo = 8'b00000000;

			//data
			@(posedge llck) vpo = 8'h01;//Cb
			@(posedge llck) vpo = 8'h02;//Yb
			@(posedge llck) vpo = 8'h03;//Cr
			@(posedge llck) vpo = 8'h04;//Yr--1

			@(posedge llck) vpo = 8'h05;//Cb
			@(posedge llck) vpo = 8'h06;//Yb
			@(posedge llck) vpo = 8'h07;//Cr
			@(posedge llck) vpo = 8'h08;//Yr--2

			@(posedge llck) vpo = 8'h09;//Cb
			@(posedge llck) vpo = 8'h0a;//Yb
			@(posedge llck) vpo = 8'h0b;//Cr
			@(posedge llck) vpo = 8'h0c;//Yr--3

			@(posedge llck) vpo = 8'h0d;//Cb
			@(posedge llck) vpo = 8'h0e;//Yb
			@(posedge llck) vpo = 8'h0f;//Cr
			@(posedge llck) vpo = 8'h10;//Yr--4

			@(posedge llck) vpo = 8'h11;//Cb
			@(posedge llck) vpo = 8'h12;//Yb
			@(posedge llck) vpo = 8'h13;//Cr
			@(posedge llck) vpo = 8'h14;//Yr--5

			@(posedge llck) vpo = 8'h15;//Cb
			@(posedge llck) vpo = 8'h16;//Yb
			@(posedge llck) vpo = 8'h17;//Cr
			@(posedge llck) vpo = 8'h18;//Yr--6

			@(posedge llck) vpo = 8'h19;//Cb
			@(posedge llck) vpo = 8'h1a;//Yb
			@(posedge llck) vpo = 8'h1b;//Cr
			@(posedge llck) vpo = 8'h1c;//Yr--7

			@(posedge llck) vpo = 8'h1d;//Cb
			@(posedge llck) vpo = 8'h1e;//Yb
			@(posedge llck) vpo = 8'h1f;//Cr
			@(posedge llck) vpo = 8'h20;//Yr--8

			@(posedge llck) vpo = 8'h21;//Cb
			@(posedge llck) vpo = 8'h22;//Yb
			@(posedge llck) vpo = 8'h23;//Cr
			@(posedge llck) vpo = 8'h24;//Yr--9

			@(posedge llck) vpo = 8'h25;//Cb
			@(posedge llck) vpo = 8'h26;//Yb
			@(posedge llck) vpo = 8'h27;//Cr
			@(posedge llck) vpo = 8'h28;//Yr--10

			@(posedge llck) vpo = 8'h29;//Cb
			@(posedge llck) vpo = 8'h3a;//Yb
			@(posedge llck) vpo = 8'h3b;//Cr
			@(posedge llck) vpo = 8'h3c;//Yr--11


			//DATA END
			@(posedge llck) vpo = 8'hff;//ff
			@(posedge llck) vpo = 8'h00;//00
			@(posedge llck) vpo = 8'h00;//00
			@(posedge llck) vpo = 8'b01110000;//end of field 1

			#20;
			
			capture = 0;



			#200;
			$finish;


			




		end	
initial   $monitor($stime,,
"error=%d dsprst=%d xreset=%d saareset=%d ARDY=%d ED_O=%d ED_OEN_O=%d SRAM_1_EA=%d SRAM_2_EA=%d SRAM_1_O_ED=%d SRAM_2_O_ED=%d",
error,dsprst,xreset,saareset,ARDY,ED_O,ED_OEN_O,SRAM_1_EA,SRAM_2_EA,SRAM_1_O_ED,SRAM_2_O_ED);
  
endmodule