📄 targ32_wrp_netlist.vhd

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    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(30),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG(4),
      B => N_103_1);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_11 is
port(
  P_BUS_EN_SIG : in std_logic_vector (7 downto 7);
  CLK_GATE : out std_logic_vector (1 downto 1);
  N_103_1 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_11;

architecture beh of CM8_11 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(1),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG(7),
      B => N_103_1);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_10 is
port(
  P_BUS_EN_SIG_0 : in std_logic_vector (6 downto 6);
  CLK_GATE : out std_logic_vector (12 downto 12);
  N_103_1 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_10;

architecture beh of CM8_10 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(12),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG_0(6),
      B => N_103_1);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_9 is
port(
  P_BUS_EN_SIG_0 : in std_logic_vector (6 downto 6);
  CLK_GATE : out std_logic_vector (14 downto 14);
  LOAD_AD_REGN_0_o3 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_9;

architecture beh of CM8_9 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(14),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG_0(6),
      B => LOAD_AD_REGN_0_o3);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_8 is
port(
  P_BUS_EN_SIG : in std_logic_vector (7 downto 7);
  CLK_GATE : out std_logic_vector (5 downto 5);
  LOAD_AD_REGN_0_o3 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_8;

architecture beh of CM8_8 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(5),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG(7),
      B => LOAD_AD_REGN_0_o3);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_7 is
port(
  P_BUS_EN_SIG : in std_logic_vector (4 downto 4);
  CLK_GATE : out std_logic_vector (27 downto 27);
  LOAD_AD_REGN_0_o3 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_7;

architecture beh of CM8_7 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(27),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG(4),
      B => LOAD_AD_REGN_0_o3);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_6 is
port(
  P_BUS_EN_SIG : in std_logic_vector (4 downto 4);
  CLK_GATE : out std_logic_vector (29 downto 29);
  LOAD_AD_REGN_0_o3 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_6;

architecture beh of CM8_6 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(29),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG(4),
      B => LOAD_AD_REGN_0_o3);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_5 is
port(
  P_BUS_EN_SIG : in std_logic_vector (7 downto 7);
  CLK_GATE : out std_logic_vector (0 downto 0);
  LOAD_AD_REGN_0_o3 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_5;

architecture beh of CM8_5 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
💿 文件大小 32 K
👤 上传用户 Numb_pqc
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

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