📄 targ32_wrp_netlist.vhd

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  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(20),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG(5),
      B => N_103_1);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_18 is
port(
  P_BUS_EN_SIG : in std_logic_vector (4 downto 4);
  CLK_GATE : out std_logic_vector (31 downto 31);
  N_103_1 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_18;

architecture beh of CM8_18 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(31),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG(4),
      B => N_103_1);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_17 is
port(
  P_BUS_EN_SIG : in std_logic_vector (7 downto 7);
  CLK_GATE : out std_logic_vector (2 downto 2);
  N_103_1 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_17;

architecture beh of CM8_17 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(2),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG(7),
      B => N_103_1);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_16 is
port(
  P_BUS_EN_SIG_0 : in std_logic_vector (6 downto 6);
  CLK_GATE : out std_logic_vector (13 downto 13);
  N_103_1 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_16;

architecture beh of CM8_16 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(13),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG_0(6),
      B => N_103_1);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_15 is
port(
  P_BUS_EN_SIG_0 : in std_logic_vector (6 downto 6);
  CLK_GATE : out std_logic_vector (15 downto 15);
  N_103_1 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_15;

architecture beh of CM8_15 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(15),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG_0(6),
      B => N_103_1);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_14 is
port(
  P_BUS_EN_SIG : in std_logic_vector (7 downto 7);
  CLK_GATE : out std_logic_vector (6 downto 6);
  N_103_1 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_14;

architecture beh of CM8_14 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(6),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG(7),
      B => N_103_1);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_13 is
port(
  P_BUS_EN_SIG : in std_logic_vector (4 downto 4);
  CLK_GATE : out std_logic_vector (28 downto 28);
  N_103_1 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_13;

architecture beh of CM8_13 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(28),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG(4),
      B => N_103_1);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_12 is
port(
  P_BUS_EN_SIG : in std_logic_vector (4 downto 4);
  CLK_GATE : out std_logic_vector (30 downto 30);
  N_103_1 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_12;

architecture beh of CM8_12 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
💿 文件大小 32 K
👤 上传用户 Numb_pqc
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

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