targ32_wrp_netlist.vhd

pcicore top files vhdl pcicore top files vhdl

--
-- Written by Synplicity
-- Sun Apr 02 14:26:07 2006
--

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity DEL_BUFF_42 is
port(
  CBE : in std_logic_vector (3 downto 3);
  CBE3_BUFF :  out std_logic);
end DEL_BUFF_42;

architecture beh of DEL_BUFF_42 is
  signal Y1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component BUFD
    port(
      Y : out std_logic;
      A : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_U2: BUFD port map (
      Y => CBE3_BUFF,
      A => Y1);
  II_U1: BUFD port map (
      Y => Y1,
      A => CBE(3));
  II_VCC_i: VCC port map (
      Y => NN_1);
  II_GND_i: GND port map (
      Y => NN_2);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_32 is
port(
  P_BUS_EN_SIG : in std_logic_vector (6 downto 6);
  N_103_0 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic;
  CLK_GATE_PAR :  out std_logic);
end CM8_32;

architecture beh of CM8_32 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE_PAR,
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG(6),
      B => N_103_0);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_31 is
port(
  P_BUS_EN_SIG : in std_logic_vector (5 downto 5);
  CLK_GATE : out std_logic_vector (22 downto 22);
  N_103_0 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_31;

architecture beh of CM8_31 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(22),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG(5),
      B => N_103_0);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_30 is
port(
  P_BUS_EN_SIG : in std_logic_vector (4 downto 4);
  CLK_GATE : out std_logic_vector (24 downto 24);
  N_103_0 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_30;

architecture beh of CM8_30 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(24),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG(4),
      B => N_103_0);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_29 is
port(
  P_BUS_EN_SIG : in std_logic_vector (7 downto 7);
  CLK_GATE : out std_logic_vector (4 downto 4);
  N_103_0 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_29;

architecture beh of CM8_29 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(4),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG(7),
      B => N_103_0);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_28 is
port(
  P_BUS_EN_SIG : in std_logic_vector (4 downto 4);
  CLK_GATE : out std_logic_vector (26 downto 26);
  N_103_0 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_28;

architecture beh of CM8_28 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(26),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG(4),
      B => N_103_0);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_27 is
port(
  P_BUS_EN_SIG : in std_logic_vector (5 downto 5);
  CLK_GATE : out std_logic_vector (17 downto 17);
  N_103_0 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_27;

architecture beh of CM8_27 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );
  end component;
  component OR2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component AND2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic  );
  end component;
  component VCC
    port(
      Y : out std_logic  );
  end component;
  component GND
    port(
      Y : out std_logic  );
  end component;
begin
  II_MAKE_MX2_2: MX2 port map (
      Y => CLK_GATE(17),
      A => Y_0,
      B => Y_1,
      S => S1);
  II_MAKE_MX2_1: MX2 port map (
      Y => Y_1,
      A => NN_1,
      B => NN_2,
      S => S0);
  II_MAKE_MX2_0: MX2 port map (
      Y => Y_0,
      A => NN_1,
      B => NN_1,
      S => S0);
  II_MAKE_OR2: OR2 port map (
      Y => S1,
      A => TRDYN_OUT,
      B => IRDYN_CLK);
  II_MAKE_AND2: AND2 port map (
      Y => S0,
      A => P_BUS_EN_SIG(5),
      B => N_103_0);
  II_VCC_i: VCC port map (
      Y => NN_2);
  II_GND_i: GND port map (
      Y => NN_1);
  NN_3 <= '0';
  NN_4 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library proasic3;
use proasic3.components.all;

entity CM8_26 is
port(
  P_BUS_EN_SIG : in std_logic_vector (5 downto 5);
  CLK_GATE : out std_logic_vector (19 downto 19);
  N_103_0 :  in std_logic;
  IRDYN_CLK :  in std_logic;
  TRDYN_OUT :  in std_logic);
end CM8_26;

architecture beh of CM8_26 is
  signal Y_0 : std_logic ;
  signal Y_1 : std_logic ;
  signal S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  signal S0 : std_logic ;
  signal NN_3 : std_logic ;
  signal NN_4 : std_logic ;
  component MX2
    port(
      Y : out std_logic;
      A : in std_logic;
      B : in std_logic;
      S : in std_logic  );