pci32_90408.vhd

pcicore top files vhdl pcicore top files vhdl

-- Main_PCI32_02.vhd
-- Main_PCI32.vhd
--
-- 创建时间：2009-03-27
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.attributes.all;
--use synplify.components.all;
--library proasic3;
--use proasic3.components.all;

entity Main_PCI32_02 is
port(
--//CorePCI PCI-BUS Interface
  CLK       :  in   std_logic;
  RST       :  in   std_logic;
  AD        :  inout std_logic_vector (31 downto 0);
  CBE       :  in   std_logic_vector (3 downto 0);
  DEVSELN   :  out  std_logic;
  FRAMEN    :  in   std_logic;
  IDSEL     :  in   std_logic;
  INTAN     :  out  std_logic;
  IRDYN     :  in   std_logic;
  PAR       :  inout std_logic;
  PERRN     :  out  std_logic;
  SERRN     :  out  std_logic;
  STOPN     :  out  std_logic;
  TRDYN     :  out  std_logic;
--//Back-End Interface
  CLKOUT    :  out  std_logic;
  CONFIG_CYC:  out  std_logic;
  DP_START  :  out  std_logic;
  DP_DONE   :  out  std_logic;
  RD_CYC    :  out  std_logic;
  WR_CYC    :  out  std_logic
--
--
  );
end Main_PCI32_02;


architecture beh of Main_PCI32_02 is


--//信号定义,状态机定义
--type    BeStates is (idle,config,mem_rd,mem_we,io_rd,io_we,begnt,extint,mem_rd_busy,mem_we_busy);
--signal  PresentState,NextState : BeStates;
--
--
--signal  BAR0_MEM_CYC : std_logic;
--signal  BAR1_CYC     : std_logic;
--signal  BE_GNT       : std_logic;
--signal  BE_REQ       : std_logic;
--signal  BUSY         : std_logic;
--signal  CONFIG_CYC   : std_logic;
--signal  DP_DONE      : std_logic;
--signal  DP_START     : std_logic;
--signal  ERROR        : std_logic;
--signal  EXT_INTN     : std_logic;
--signal  MEM_ADD      : std_logic_vector (13 downto 0);
--signal  MEM_DATA_IN  : std_logic_vector (31 downto 0);
--signal  MEM_DATA_OUT : std_logic_vector (31 downto 0);
--signal  MEM_DATA_OE  : std_logic;
--signal  PIPE_FULL_CNT: std_logic_vector (2 downto 0);
--signal  RD_BE_NOW    : std_logic;
--signal  RD_BE_RDY    : std_logic;
--signal  RD_CYC       : std_logic;
--signal  WR_BE_NOW    : std_logic_vector (3 downto 0);
--signal  WR_BE_RDY    : std_logic;
--signal  WR_CYC       : std_logic;
--
--
--//PCI32 CORE元件
  component  TARG32_WRP
  port(
  CLK_OUT :  out std_logic;
  CLK :  in std_logic;
  RST :  in std_logic;
  AD : inout std_logic_vector (31 downto 0);
  CBE : in std_logic_vector (3 downto 0);
  DEVSELN :  out std_logic;
  FRAMEN :  in std_logic;
  IDSEL :  in std_logic;
  INTAN :  out std_logic;
  IRDYN :  in std_logic;
  PAR :  inout std_logic;
  PERRN :  out std_logic;
  SERRN :  out std_logic;
  STOPN :  out std_logic;
  TRDYN :  out std_logic;
  BAR0_MEM_CYC :  out std_logic;
  BAR1_CYC :  out std_logic;
  BE_GNT :  out std_logic;
  BE_REQ :  in std_logic;
  BUSY :  in std_logic;
  CONFIG_CYC :  out std_logic;
  DP_DONE :  out std_logic;
  DP_START :  out std_logic;
  ERROR :  in std_logic;
  EXT_INTN :  in std_logic;
  MEM_ADD : out std_logic_vector (13 downto 0);
  MEM_DATA_IN : in std_logic_vector (31 downto 0);
  MEM_DATA_OUT : out std_logic_vector (31 downto 0);
  MEM_DATA_OE :  out std_logic;
  PIPE_FULL_CNT : in std_logic_vector (2 downto 0);
  RD_BE_NOW :  out std_logic;
  RD_BE_RDY :  in std_logic;
  RD_CYC :  out std_logic;
  WR_BE_NOW : out std_logic_vector (3 downto 0);
  WR_BE_RDY :  in std_logic;
  WR_CYC :  out std_logic);
  end component;
--attribute syn_black_box of TARG32_WRP : component is true;
--attribute syn_black_box of beh : architecture is true;
--
--
begin
--
--
  PCI32_CORE: TARG32_WRP port map (
 --
  CLK_OUT   =>  CLKOUT,
  CLK       =>  CLK,
  RST       =>  RST,
  AD        =>  AD,
  CBE       =>  CBE,
  DEVSELN   =>  DEVSELN,
  FRAMEN    =>  FRAMEN,
  IDSEL     =>  IDSEL,
  INTAN     =>  INTAN,
  IRDYN     =>  IRDYN,
  PAR       =>  PAR,
  PERRN     =>  PERRN,
  SERRN     =>  SERRN,
  STOPN     =>  STOPN,
  TRDYN     =>  TRDYN,
  --//  
  BAR0_MEM_CYC  =>  open,
  BAR1_CYC      =>  open,
  BE_GNT        =>  open,
  BE_REQ        =>  '0',
  BUSY          =>  '0',
  CONFIG_CYC    =>  CONFIG_CYC,--open,
  DP_DONE       =>  DP_DONE,   --open,
  DP_START      =>  DP_START,  --open,
  ERROR         =>  '0',
  EXT_INTN      =>  '1',
  MEM_ADD       =>  open,
  MEM_DATA_IN   =>  (others=>'0'),
  MEM_DATA_OUT  =>  open,
  MEM_DATA_OE   =>  open,
  PIPE_FULL_CNT =>  (others=>'0'),
  RD_BE_NOW     =>  open,
  RD_BE_RDY     =>  '0',
  RD_CYC        =>  RD_CYC,    --open,
  WR_BE_NOW     =>  open,
  WR_BE_RDY     =>  '0',
  WR_CYC        =>  WR_CYC     --open
  );
--
--
--
--
--信号上下拉
--Core输入上下拉
--PIPE_FULL_CNT <=(others=>'0');
--RD_BE_RDY     <='1';--后端读准备好
--WR_BE_RDY     <='1';--后端写准备好
--MEM_DATA_IN   <=(others=>'0');
--BE_REQ        <='0';--后端请求  
--BUSY          <='0';--后端忙
--ERROR         <='0';--后端错误
--EXT_INTN      <='1';--后端中断