generale.twr

simple thermometr in vhdl

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Release 9.2i Trace 
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

C:\Xilinx92i\bin\nt\trce.exe -ise
C:/Documents and Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA/VGAterm/VGAterm.ise
-intstyle ise -e 3 -s 5 -xml generale generale.ncd -o generale.twr generale.pcf
-ucf generale.ucf

Design file:              generale.ncd
Physical constraint file: generale.pcf
Device,package,speed:     xc2s50,tq144,-5 (PRODUCTION 1.27 2007-04-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk88
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk88          |    5.757|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Sun Dec 02 20:43:19 2007 
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 77 MB