coregen.log

simple thermometr in vhdl

# Xilinx CORE Generator 6.1i
# User = ferluga
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\JernejAles\Termometro_visualizzato_su_VGA\VGAterm\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=E:\JernejAles\Termometro_visualizzato_su_VGA\VGAterm
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=E:\JernejAles\Termometro_visualizzato_su_VGA\VGAterm
SETPROJECT .
Set current Project to E:\JernejAles\Termometro_visualizzato_su_VGA\VGAterm
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1484
XIPCPJSENDCORES spartan2