__projnav.log

simple thermometr in vhdl

    Found 10-bit comparator less for signal <$n0004> created at line 33.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   1 Multiplexer(s).
Unit <scrittura_seriale> synthesized.


Synthesizing Unit <selettor>.
    Related source file is e:/jernejales/termometro_visualizzato_su_vga/vgaterm/Selettore.vhd.
    Found 46-bit register for signal <st_out>.
    Summary:
	inferred  46 D-type flip-flop(s).
Unit <selettor> synthesized.


Synthesizing Unit <nic>.
    Related source file is e:/jernejales/termometro_visualizzato_su_vga/vgaterm/zero.vhd.
    Found 46-bit register for signal <D_OUT>.
    Summary:
	inferred  46 D-type flip-flop(s).
Unit <nic> synthesized.


Synthesizing Unit <devet>.
    Related source file is e:/jernejales/termometro_visualizzato_su_vga/vgaterm/nove.vhd.
    Found 46-bit register for signal <D_OUT>.
    Summary:
	inferred  46 D-type flip-flop(s).
Unit <devet> synthesized.


Synthesizing Unit <osem>.
    Related source file is e:/jernejales/termometro_visualizzato_su_vga/vgaterm/otto.vhd.
    Found 46-bit register for signal <D_OUT>.
    Summary:
	inferred  46 D-type flip-flop(s).
Unit <osem> synthesized.


Synthesizing Unit <sedem>.
    Related source file is e:/jernejales/termometro_visualizzato_su_vga/vgaterm/sette.vhd.
    Found 46-bit register for signal <D_OUT>.
    Summary:
	inferred  46 D-type flip-flop(s).
Unit <sedem> synthesized.


Synthesizing Unit <sest>.
    Related source file is e:/jernejales/termometro_visualizzato_su_vga/vgaterm/sei.vhd.
    Found 46-bit register for signal <D_OUT>.
    Summary:
	inferred  46 D-type flip-flop(s).
Unit <sest> synthesized.


Synthesizing Unit <pet>.
    Related source file is e:/jernejales/termometro_visualizzato_su_vga/vgaterm/cinque.vhd.
    Found 46-bit register for signal <D_OUT>.
    Summary:
	inferred  46 D-type flip-flop(s).
Unit <pet> synthesized.


Synthesizing Unit <stiri>.
    Related source file is e:/jernejales/termometro_visualizzato_su_vga/vgaterm/quattro.vhd.
    Found 46-bit register for signal <D_OUT>.
    Summary:
	inferred  46 D-type flip-flop(s).
Unit <stiri> synthesized.


Synthesizing Unit <tri>.
    Related source file is e:/jernejales/termometro_visualizzato_su_vga/vgaterm/tre.vhd.
    Found 46-bit register for signal <D_OUT>.
    Summary:
	inferred  46 D-type flip-flop(s).
Unit <tri> synthesized.


Synthesizing Unit <dva>.
    Related source file is e:/jernejales/termometro_visualizzato_su_vga/vgaterm/due.vhd.
    Found 46-bit register for signal <D_OUT>.
    Summary:
	inferred  46 D-type flip-flop(s).
Unit <dva> synthesized.


Synthesizing Unit <ena>.
    Related source file is e:/jernejales/termometro_visualizzato_su_vga/vgaterm/uno.vhd.
    Found 46-bit register for signal <D_OUT>.
    Summary:
	inferred  46 D-type flip-flop(s).
Unit <ena> synthesized.


Synthesizing Unit <generale>.
    Related source file is e:/jernejales/termometro_visualizzato_su_vga/vgaterm/Generale.vhf.
Unit <generale> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 18
  1-bit register                   : 5
  6-bit register                   : 1
  10-bit register                  : 1
  46-bit register                  : 11
# Counters                         : 5
  29-bit up counter                : 1
  10-bit up counter                : 3
  9-bit up counter                 : 1
# Multiplexers                     : 1
  1-bit 46-to-1 multiplexer        : 1
# Comparators                      : 16
  11-bit comparator less           : 8
  11-bit comparator greatequal     : 6
  11-bit comparator lessequal      : 1
  10-bit comparator less           : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <D_OUT_45> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_0> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_1> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_2> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_3> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_4> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_5> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_6> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_7> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_8> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_9> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_37> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_38> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_39> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_40> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_41> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_42> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_43> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_44> (without init value) is constant in block <ena>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_45> (without init value) is constant in block <tri>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_0> (without init value) is constant in block <tri>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_1> (without init value) is constant in block <tri>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_2> (without init value) is constant in block <tri>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_3> (without init value) is constant in block <tri>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_44> (without init value) is constant in block <tri>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_45> (without init value) is constant in block <pet>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_0> (without init value) is constant in block <pet>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_1> (without init value) is constant in block <pet>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_2> (without init value) is constant in block <pet>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_3> (without init value) is constant in block <pet>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_44> (without init value) is constant in block <pet>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_0> (without init value) is constant in block <sest>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_45> (without init value) is constant in block <sedem>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_0> (without init value) is constant in block <sedem>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_1> (without init value) is constant in block <sedem>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_45> (without init value) is constant in block <osem>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_0> (without init value) is constant in block <osem>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_1> (without init value) is constant in block <osem>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_2> (without init value) is constant in block <osem>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_44> (without init value) is constant in block <osem>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_0> (without init value) is constant in block <devet>.
WARNING:Xst:1710 - FF/Latch  <D_OUT_0> (without init value) is constant in block <nic>.

Optimizing unit <generale> ...

Optimizing unit <ena> ...

Optimizing unit <dva> ...

Optimizing unit <tri> ...

Optimizing unit <stiri> ...

Optimizing unit <pet> ...

Optimizing unit <sest> ...

Optimizing unit <sedem> ...

Optimizing unit <osem> ...

Optimizing unit <devet> ...

Optimizing unit <nic> ...

Optimizing unit <selettor> ...

Optimizing unit <sinc_h> ...

Optimizing unit <sinc_v> ...

Optimizing unit <FTC_MXILINX_generale> ...
Loading device for application Xst from file 'v50.nph' in environment E:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Register XLXI_13_rgb_4 equivalent to XLXI_13_rgb_0 has been removed
Register XLXI_13_rgb_2 equivalent to XLXI_13_rgb_0 has been removed
Register XLXI_13_rgb_3 equivalent to XLXI_13_rgb_0 has been removed
Register XLXI_13_rgb_1 equivalent to XLXI_13_rgb_0 has been removed
Register XLXI_13_rgb_5 equivalent to XLXI_13_rgb_0 has been removed
Found area constraint ratio of 100 (+ 5) on block generale, actual ratio is 259.
Optimizing block <generale> to meet ratio 100 (+ 5) of 768 slices :
WARNING:Xst - Area constraint could not be met for block <generale>, final ratio is 232.
FlipFlop XLXI_21_COUNT_27 has been replicated 7 time(s)
FlipFlop XLXI_21_COUNT_28 has been replicated 3 time(s)
FlipFlop XLXI_21_COUNT_26 has been replicated 5 time(s)
FlipFlop XLXI_14_lin_20 has been replicated 1 time(s)
FlipFlop XLXI_14_lin_21 has been replicated 1 time(s)
FlipFlop XLXI_14_lin_22 has been replicated 1 time(s)
FlipFlop XLXI_14_lin_23 has been replicated 1 time(s)
FlipFlop XLXI_14_lin_24 has been replicated 1 time(s)
FlipFlop XLXI_14_lin_25 has been replicated 1 time(s)
FlipFlop XLXI_14_lin_26 has been replicated 1 time(s)
FlipFlop XLXI_14_lin_27 has been replicated 1 time(s)
FlipFlop XLXI_21_COUNT_25 has been replicated 10 time(s)
FlipFlop XLXI_21_COUNT_26 has been replicated 1 time(s)
FlipFlop XLXI_21_COUNT_27 has been replicated 1 time(s)
FlipFlop XLXI_21_COUNT_28 has been replicated 1 time(s)
FlipFlop XLXI_13_dot1_0 has been replicated 1 time(s)
FlipFlop XLXI_14_lin_20 has been replicated 4 time(s)
FlipFlop XLXI_14_lin_21 has been replicated 4 time(s)
FlipFlop XLXI_14_lin_22 has been replicated 4 time(s)
FlipFlop XLXI_14_lin_23 has been replicated 3 time(s)
FlipFlop XLXI_14_lin_24 has been replicated 2 time(s)
FlipFlop XLXI_14_lin_25 has been replicated 2 time(s)
FlipFlop XLXI_14_lin_26 has been replicated 2 time(s)
FlipFlop XLXI_14_lin_27 has been replicated 2 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-5 

 Number of Slices:                    1795  out of    768   233% (*) 
 Number of Slice Flip Flops:           609  out of   1536    39%  
 Number of 4 input LUTs:              3142  out of   1536   204% (*) 
 Number of bonded IOBs:                  8  out of     96     8%  
 Number of GCLKs:                        1  out of      4    25%  

WARNING:Xst:1336 -  (*) More than 100% of Device resources are used


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk88                              | BUFGP                  | 1     |
XLXI_15/I_36_35:Q                  | NONE                   | 556   |
XLXI_13_end_l:Q                    | NONE                   | 52    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 12.860ns (Maximum Frequency: 77.761MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 8.699ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
e:\jernejales\termometro_visualizzato_su_vga\vgaterm/_ngo -i -p xc2s50-tq144-5
generale.ngc generale.ngd 

Reading NGO file
"e:/jernejales/termometro_visualizzato_su_vga/vgaterm/generale.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'XLXN_50' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Total memory usage is 39984 kilobytes

Writing NGD file "generale.ngd" ...

Writing NGDBUILD log file "generale.bld"...

NGDBUILD done.
Completed process "Translate".



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