__projnav.log

simple thermometr in vhdl

Release 6.1i - spl2sym G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
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Started process "Create Schematic Symbol".

Compiling vhdl file
e:/jernejales/termometro_visualizzato_su_vga/vgaterm/sinc_H.vhd in Library work.
Entity <sinc_h> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.1i - spl2sym G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file
e:/jernejales/termometro_visualizzato_su_vga/vgaterm/sinc_v.vhd in Library work.
Entity <sinc_v> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.1i - spl2sym G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file
e:/jernejales/termometro_visualizzato_su_vga/vgaterm/quattro.vhd in Library
work.
Entity <stiri> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.1i - spl2sym G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/jernejales/termometro_visualizzato_su_vga/vgaterm/tre.vhd
in Library work.
Entity <tri> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.1i - spl2sym G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file
e:/jernejales/termometro_visualizzato_su_vga/vgaterm/Scrittura_seriale.vhd in
Library work.
WARNING:HDLParsers:3350 -
   e:/jernejales/termometro_visualizzato_su_vga/vgaterm/Scrittura_seriale.vhd
   Line 17. Null range: 0 downto 45
Entity <scrittura_seriale> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.1i - spl2sym G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file
e:/jernejales/termometro_visualizzato_su_vga/vgaterm/sinc_H.vhd in Library work.
Entity <sinc_h> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.1i - spl2sym G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file
e:/jernejales/termometro_visualizzato_su_vga/vgaterm/contatore.vhd in Library
work.
Entity <kontator> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.1i - spl2sym G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.1i - sch2vhdl G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/jernejales/termometro_visualizzato_su_vga/vgaterm/uno.vhd in Library work.
Architecture behavioral of Entity ena is up to date.
Compiling vhdl file e:/jernejales/termometro_visualizzato_su_vga/vgaterm/due.vhd in Library work.
Architecture behavioral of Entity dva is up to date.
Compiling vhdl file e:/jernejales/termometro_visualizzato_su_vga/vgaterm/tre.vhd in Library work.
Architecture behavioral of Entity tri is up to date.
Compiling vhdl file e:/jernejales/termometro_visualizzato_su_vga/vgaterm/quattro.vhd in Library work.
Architecture behavioral of Entity stiri is up to date.
Compiling vhdl file e:/jernejales/termometro_visualizzato_su_vga/vgaterm/cinque.vhd in Library work.
Architecture behavioral of Entity pet is up to date.
Compiling vhdl file e:/jernejales/termometro_visualizzato_su_vga/vgaterm/sei.vhd in Library work.
Architecture behavioral of Entity sest is up to date.
Compiling vhdl file e:/jernejales/termometro_visualizzato_su_vga/vgaterm/sette.vhd in Library work.
Architecture behavioral of Entity sedem is up to date.
Compiling vhdl file e:/jernejales/termometro_visualizzato_su_vga/vgaterm/otto.vhd in Library work.
Architecture behavioral of Entity osem is up to date.
Compiling vhdl file e:/jernejales/termometro_visualizzato_su_vga/vgaterm/nove.vhd in Library work.
Architecture behavioral of Entity devet is up to date.
Compiling vhdl file e:/jernejales/termometro_visualizzato_su_vga/vgaterm/zero.vhd in Library work.
Architecture behavioral of Entity nic is up to date.
Compiling vhdl file e:/jernejales/termometro_visualizzato_su_vga/vgaterm/Selettore.vhd in Library work.
Architecture behavioral of Entity selettor is up to date.
Compiling vhdl file e:/jernejales/termometro_visualizzato_su_vga/vgaterm/Scrittura_seriale.vhd in Library work.
WARNING:HDLParsers:3350 - e:/jernejales/termometro_visualizzato_su_vga/vgaterm/Scrittura_seriale.vhd Line 17. Null range: 0 downto 45
Architecture behavioral of Entity scrittura_seriale is up to date.
Compiling vhdl file e:/jernejales/termometro_visualizzato_su_vga/vgaterm/sinc_H.vhd in Library work.
Architecture behavioral of Entity sinc_h is up to date.
Compiling vhdl file e:/jernejales/termometro_visualizzato_su_vga/vgaterm/sinc_v.vhd in Library work.
Architecture behavioral of Entity sinc_v is up to date.
Compiling vhdl file e:/jernejales/termometro_visualizzato_su_vga/vgaterm/contatore.vhd in Library work.
Architecture behavioral of Entity kontator is up to date.
Compiling vhdl file e:/jernejales/termometro_visualizzato_su_vga/vgaterm/Generale.vhf in Library work.
Entity <FTC_MXILINX_generale> (Architecture <BEHAVIORAL>) compiled.
Entity <generale> (Architecture <BEHAVIORAL>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <generale> (Architecture <BEHAVIORAL>).
WARNING:Xst:1541 - e:/jernejales/termometro_visualizzato_su_vga/vgaterm/Generale.vhf line 278: Different binding for component: <scrittura_seriale>. Port <data> does not match.
    Set user-defined property "HU_SET =  XLXI_15_0" for instance <XLXI_15> in unit <generale>.
Entity <generale> analyzed. Unit <generale> generated.

Analyzing Entity <ena> (Architecture <behavioral>).
Entity <ena> analyzed. Unit <ena> generated.

Analyzing Entity <dva> (Architecture <behavioral>).
Entity <dva> analyzed. Unit <dva> generated.

Analyzing Entity <tri> (Architecture <behavioral>).
Entity <tri> analyzed. Unit <tri> generated.

Analyzing Entity <stiri> (Architecture <behavioral>).
Entity <stiri> analyzed. Unit <stiri> generated.

Analyzing Entity <pet> (Architecture <behavioral>).
Entity <pet> analyzed. Unit <pet> generated.

Analyzing Entity <sest> (Architecture <behavioral>).
Entity <sest> analyzed. Unit <sest> generated.

Analyzing Entity <sedem> (Architecture <behavioral>).
Entity <sedem> analyzed. Unit <sedem> generated.

Analyzing Entity <osem> (Architecture <behavioral>).
Entity <osem> analyzed. Unit <osem> generated.

Analyzing Entity <devet> (Architecture <behavioral>).
Entity <devet> analyzed. Unit <devet> generated.

Analyzing Entity <nic> (Architecture <behavioral>).
Entity <nic> analyzed. Unit <nic> generated.

Analyzing Entity <selettor> (Architecture <behavioral>).
Entity <selettor> analyzed. Unit <selettor> generated.

Analyzing Entity <scrittura_seriale> (Architecture <behavioral>).
WARNING:Xst:790 - e:/jernejales/termometro_visualizzato_su_vga/vgaterm/Scrittura_seriale.vhd line 33: Index value(s) does not match array range, simulation mismatch.
Entity <scrittura_seriale> analyzed. Unit <scrittura_seriale> generated.

Analyzing Entity <sinc_h> (Architecture <behavioral>).
Entity <sinc_h> analyzed. Unit <sinc_h> generated.

Analyzing Entity <sinc_v> (Architecture <behavioral>).
Entity <sinc_v> analyzed. Unit <sinc_v> generated.

Analyzing Entity <FTC_MXILINX_generale> (Architecture <behavioral>).
    Set user-defined property "INIT =  0" for unit <FDC>.
    Set user-defined property "RLOC =  R0C0.S0" for instance <I_36_35> in unit <FTC_MXILINX_generale>.
Entity <FTC_MXILINX_generale> analyzed. Unit <FTC_MXILINX_generale> generated.

Analyzing Entity <kontator> (Architecture <behavioral>).
Entity <kontator> analyzed. Unit <kontator> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <kontator>.
    Related source file is e:/jernejales/termometro_visualizzato_su_vga/vgaterm/contatore.vhd.
    Found 29-bit up counter for signal <COUNT>.
    Summary:
	inferred   1 Counter(s).
Unit <kontator> synthesized.


Synthesizing Unit <FTC_MXILINX_generale>.
    Related source file is e:/jernejales/termometro_visualizzato_su_vga/vgaterm/Generale.vhf.
Unit <FTC_MXILINX_generale> synthesized.


Synthesizing Unit <sinc_v>.
    Related source file is e:/jernejales/termometro_visualizzato_su_vga/vgaterm/sinc_v.vhd.
    Found 9-bit up counter for signal <lin>.
    Found 1-bit register for signal <vs>.
    Found 1-bit register for signal <blan>.
    Found 11-bit comparator less for signal <$n0008> created at line 64.
    Found 11-bit comparator greatequal for signal <$n0009> created at line 52.
    Found 11-bit comparator less for signal <$n0010> created at line 52.
    Found 11-bit comparator greatequal for signal <$n0011> created at line 56.
    Found 11-bit comparator less for signal <$n0012> created at line 56.
    Found 11-bit comparator greatequal for signal <$n0013> created at line 60.
    Found 11-bit comparator less for signal <$n0014> created at line 60.
    Found 10-bit up counter for signal <count>.
    Summary:
	inferred   2 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   7 Comparator(s).
Unit <sinc_v> synthesized.


Synthesizing Unit <sinc_h>.
    Related source file is e:/jernejales/termometro_visualizzato_su_vga/vgaterm/sinc_H.vhd.
WARNING:Xst:1778 - Inout <dot1> is assigned but never used.
    Found 1-bit register for signal <hs>.
    Found 1-bit register for signal <end_l>.
    Found 10-bit register for signal <dot1>.
    Found 6-bit register for signal <rgb>.
    Found 11-bit comparator less for signal <$n0014> created at line 91.
    Found 11-bit comparator greatequal for signal <$n0059> created at line 65.
    Found 11-bit comparator less for signal <$n0060> created at line 65.
    Found 11-bit comparator greatequal for signal <$n0061> created at line 69.
    Found 11-bit comparator less for signal <$n0062> created at line 69.
    Found 11-bit comparator greatequal for signal <$n0063> created at line 86.
    Found 11-bit comparator less for signal <$n0064> created at line 86.
    Found 11-bit comparator lessequal for signal <$n0065> created at line 72.
    Found 10-bit up counter for signal <count>.
    Found 10-bit up counter for signal <dot>.
    Summary:
	inferred   2 Counter(s).
	inferred  18 D-type flip-flop(s).
	inferred   8 Comparator(s).
Unit <sinc_h> synthesized.


Synthesizing Unit <scrittura_seriale>.
    Related source file is e:/jernejales/termometro_visualizzato_su_vga/vgaterm/Scrittura_seriale.vhd.
    Found 1-bit register for signal <pixel>.
    Found 1-bit 46-to-1 multiplexer for signal <$n0001> created at line 33.