📄 generale.syr
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AsynReset = false width = 2Analyzing hierarchy for entity <JCounter> in library <work> (architecture <arch1>) with generics. AsynReset = true width = 10Analyzing hierarchy for entity <BitReg> in library <work> (architecture <arch1>) with generics. numBits = 8Analyzing hierarchy for entity <ByteReg> in library <work> (architecture <arch1>) with generics. numBytes = 6=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <generale> in library <work> (Architecture <behavioral>). Set user-defined property "HU_SET = XLXI_15_0" for instance <XLXI_15> in unit <generale>.Entity <generale> analyzed. Unit <generale> generated.Analyzing Entity <FTC_MXILINX_generale> in library <work> (Architecture <behavioral>). Set user-defined property "INIT = 0" for instance <I_36_35> in unit <FTC_MXILINX_generale>. Set user-defined property "RLOC = R0C0.S0" for instance <I_36_35> in unit <FTC_MXILINX_generale>.Entity <FTC_MXILINX_generale> analyzed. Unit <FTC_MXILINX_generale> generated.Analyzing Entity <caratteri> in library <work> (Architecture <behavioral>).Entity <caratteri> analyzed. Unit <caratteri> generated.Analyzing Entity <devet> in library <work> (Architecture <behavioral>).Entity <devet> analyzed. Unit <devet> generated.Analyzing Entity <dva> in library <work> (Architecture <behavioral>).Entity <dva> analyzed. Unit <dva> generated.Analyzing Entity <ena> in library <work> (Architecture <behavioral>).Entity <ena> analyzed. Unit <ena> generated.Analyzing Entity <tri> in library <work> (Architecture <behavioral>).Entity <tri> analyzed. Unit <tri> generated.Analyzing Entity <stiri> in library <work> (Architecture <behavioral>).Entity <stiri> analyzed. Unit <stiri> generated.Analyzing Entity <pet> in library <work> (Architecture <behavioral>).Entity <pet> analyzed. Unit <pet> generated.Analyzing Entity <sest> in library <work> (Architecture <behavioral>).Entity <sest> analyzed. Unit <sest> generated.Analyzing Entity <sedem> in library <work> (Architecture <behavioral>).Entity <sedem> analyzed. Unit <sedem> generated.Analyzing Entity <osem> in library <work> (Architecture <behavioral>).Entity <osem> analyzed. Unit <osem> generated.Analyzing Entity <nic> in library <work> (Architecture <behavioral>).Entity <nic> analyzed. Unit <nic> generated.Analyzing Entity <selettor> in library <work> (Architecture <behavioral>).Entity <selettor> analyzed. Unit <selettor> generated.Analyzing Entity <meno> in library <work> (Architecture <behavioral>).Entity <meno> analyzed. Unit <meno> generated.Analyzing Entity <punto> in library <work> (Architecture <behavioral>).Entity <punto> analyzed. Unit <punto> generated.Analyzing Entity <gradi> in library <work> (Architecture <behavioral>).Entity <gradi> analyzed. Unit <gradi> generated.Analyzing Entity <pos_sel> in library <work> (Architecture <behavioral>).Entity <pos_sel> analyzed. Unit <pos_sel> generated.Analyzing Entity <vga> in library <work> (Architecture <behavioral>).Entity <vga> analyzed. Unit <vga> generated.Analyzing Entity <scrittura_seriale> in library <work> (Architecture <behavioral>).Entity <scrittura_seriale> analyzed. Unit <scrittura_seriale> generated.Analyzing Entity <sinc_h> in library <work> (Architecture <behavioral>).Entity <sinc_h> analyzed. Unit <sinc_h> generated.Analyzing Entity <sinc_v> in library <work> (Architecture <behavioral>).Entity <sinc_v> analyzed. Unit <sinc_v> generated.Analyzing Entity <swap> in library <work> (Architecture <behavioral>).Entity <swap> analyzed. Unit <swap> generated.Analyzing Entity <termometro> in library <work> (Architecture <behavioral>).WARNING:Xst:753 - "C:/Documents and Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA_vers.ISE_9.2i/VGAterm/termometro.vhf" line 107: Unconnected output port 'data_valid' of component 'onewire_iface'.WARNING:Xst:753 - "C:/Documents and Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA_vers.ISE_9.2i/VGAterm/termometro.vhf" line 107: Unconnected output port 'crc_ok' of component 'onewire_iface'.WARNING:Xst:753 - "C:/Documents and Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA_vers.ISE_9.2i/VGAterm/termometro.vhf" line 107: Unconnected output port 'data' of component 'onewire_iface'.Entity <termometro> analyzed. Unit <termometro> generated.Analyzing Entity <complemento2> in library <work> (Architecture <behavioral>).WARNING:Xst:819 - "C:/Documents and Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA_vers.ISE_9.2i/VGAterm/complemento2.vhd" line 26: The following signals are missing in the process sensitivity list: data.Entity <complemento2> analyzed. Unit <complemento2> generated.Analyzing Entity <estrai_cifre> in library <work> (Architecture <behavioral>).WARNING:Xst:753 - "C:/Documents and Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA_vers.ISE_9.2i/VGAterm/estrai_cifre.vhf" line 66: Unconnected output port 'Q' of component 'div_rest_nat'.Entity <estrai_cifre> analyzed. Unit <estrai_cifre> generated.Analyzing Entity <costante_dieci> in library <work> (Architecture <behavioral>).Entity <costante_dieci> analyzed. Unit <costante_dieci> generated.Analyzing Entity <div_rest_nat> in library <work> (Architecture <div_arch>).Entity <div_rest_nat> analyzed. Unit <div_rest_nat> generated.Analyzing Entity <restoring_cell> in library <work> (Architecture <cel_arch>).Entity <restoring_cell> analyzed. Unit <restoring_cell> generated.Analyzing generic Entity <onewire_iface> in library <work> (Architecture <rtl>). ADD_PULLUP = true CLK_DIV = 12 CheckCRC = falseWARNING:Xst:2211 - "C:/Documents and Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA_vers.ISE_9.2i/VGAterm/onewire_iface.vhd" line 196: Instantiating black box module <PULLUP>.Entity <onewire_iface> analyzed. Unit <onewire_iface> generated.Analyzing generic Entity <clk_divider> in library <work> (Architecture <rtl>). CLK_DIV = 12WARNING:Xst:2211 - "C:/Documents and Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA_vers.ISE_9.2i/VGAterm/clk_div.vhd" line 141: Instantiating black box module <SRL16>.WARNING:Xst:2211 - "C:/Documents and Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA_vers.ISE_9.2i/VGAterm/clk_div.vhd" line 155: Instantiating black box module <SRL16>.Entity <clk_divider> analyzed. Unit <clk_divider> generated.Analyzing generic Entity <onewire_master> in library <work> (Architecture <rtl>). CheckCRC = falseWARNING:Xst:2211 - "C:/Documents and Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA_vers.ISE_9.2i/VGAterm/onewire_master.vhd" line 413: Instantiating black box module <IOBUF>.WARNING:Xst:819 - "C:/Documents and Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA_vers.ISE_9.2i/VGAterm/onewire_master.vhd" line 670: The following signals are missing in the process sensitivity list: conv_ok.Entity <onewire_master> analyzed. Unit <onewire_master> generated.Analyzing generic Entity <SHReg.1> in library <work> (Architecture <arch1>). AsynReset = false circular = true width = 8Entity <SHReg.1> analyzed. Unit <SHReg.1> generated.Analyzing generic Entity <SHReg.2> in library <work> (Architecture <arch1>). AsynReset = false circular = false width = 8Entity <SHReg.2> analyzed. Unit <SHReg.2> generated.Analyzing generic Entity <JCounter.1> in library <work> (Architecture <arch1>). AsynReset = false width = 2Entity <JCounter.1> analyzed. Unit <JCounter.1> generated.Analyzing generic Entity <JCounter.2> in library <work> (Architecture <arch1>). AsynReset = true width = 10Entity <JCounter.2> analyzed. Unit <JCounter.2> generated.Analyzing generic Entity <BitReg> in library <work> (Architecture <arch1>). numBits = 8Entity <BitReg> analyzed. Unit <BitReg> generated.Analyzing generic Entity <ByteReg> in library <work> (Architecture <arch1>). numBytes = 6Entity <ByteReg> analyzed. Unit <ByteReg> generated.Analyzing Entity <sincronismo> in library <work> (Architecture <behavioral>).Entity <sincronismo> analyzed. Unit <sincronismo> generated.Analyzing Entity <contatore21bit> in library <work> (Architecture <behavioral>).Entity <contatore21bit> analyzed. Unit <contatore21bit> generated.=========================================================================* HDL Synthesis *=========================================================================
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