vga.vhf

simple thermometr in vhdl

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 9.2i
--  \   \         Application : sch2vhdl
--  /   /         Filename : VGA.vhf
-- /___/   /\     Timestamp : 12/04/2007 11:23:31
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: C:\Xilinx92i\bin\nt\sch2vhdl.exe -intstyle ise -family spartan2 -flat -suppress -w "C:/Documents and Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA_vers.ISE_9.2i/VGAterm/vga.sch" VGA.vhf
--Design Name: vga
--Device: spartan2
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesis and simulted, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity vga is
   port ( clk       : in    std_logic; 
          colore    : in    std_logic; 
          dato      : in    std_logic_vector (33 downto 0); 
          fine      : in    std_logic_vector (9 downto 0); 
          inizio    : in    std_logic_vector (9 downto 0); 
          hs        : out   std_logic; 
          line_add  : out   std_logic_vector (8 downto 0); 
          pixel_add : out   std_logic_vector (9 downto 0); 
          RGB       : out   std_logic_vector (5 downto 0); 
          vs        : out   std_logic);
end vga;

architecture BEHAVIORAL of vga is
   signal XLXN_1          : std_logic;
   signal XLXN_2          : std_logic;
   signal XLXN_3          : std_logic_vector (33 downto 0);
   signal XLXN_11         : std_logic;
   signal pixel_add_DUMMY : std_logic_vector (9 downto 0);
   signal line_add_DUMMY  : std_logic_vector (8 downto 0);
   component scrittura_seriale
      port ( clk       : in    std_logic; 
             pixel_add : in    std_logic_vector (9 downto 0); 
             data      : in    std_logic_vector (33 downto 0); 
             inizio    : in    std_logic_vector (9 downto 0); 
             fine      : in    std_logic_vector (9 downto 0); 
             pixel     : out   std_logic);
   end component;
   
   component sinc_h
      port ( clk   : in    std_logic; 
             pixel : in    std_logic; 
             color : in    std_logic; 
             bla   : in    std_logic; 
             dot1  : inout std_logic_vector (9 downto 0); 
             end_l : out   std_logic; 
             hs    : out   std_logic; 
             rgb   : out   std_logic_vector (5 downto 0));
   end component;
   
   component sinc_v
      port ( clk  : in    std_logic; 
             lin  : inout std_logic_vector (8 downto 0); 
             vs   : out   std_logic; 
             blan : out   std_logic);
   end component;
   
   component swap
      port ( ingr : in    std_logic_vector (33 downto 0); 
             usci : out   std_logic_vector (33 downto 0));
   end component;
   
begin
   line_add(8 downto 0) <= line_add_DUMMY(8 downto 0);
   pixel_add(9 downto 0) <= pixel_add_DUMMY(9 downto 0);
   XLXI_1 : scrittura_seriale
      port map (clk=>clk,
                data(33 downto 0)=>XLXN_3(33 downto 0),
                fine(9 downto 0)=>fine(9 downto 0),
                inizio(9 downto 0)=>inizio(9 downto 0),
                pixel_add(9 downto 0)=>pixel_add_DUMMY(9 downto 0),
                pixel=>XLXN_2);
   
   XLXI_2 : sinc_h
      port map (bla=>XLXN_11,
                clk=>clk,
                color=>colore,
                pixel=>XLXN_2,
                end_l=>XLXN_1,
                hs=>hs,
                rgb(5 downto 0)=>RGB(5 downto 0),
                dot1(9 downto 0)=>pixel_add_DUMMY(9 downto 0));
   
   XLXI_3 : sinc_v
      port map (clk=>XLXN_1,
                blan=>XLXN_11,
                vs=>vs,
                lin(8 downto 0)=>line_add_DUMMY(8 downto 0));
   
   XLXI_4 : swap
      port map (ingr(33 downto 0)=>dato(33 downto 0),
                usci(33 downto 0)=>XLXN_3(33 downto 0));
   
end BEHAVIORAL;