divisore_base2.vhd

simple thermometr in vhdl

----------------------------------------------------------------------------------
-- Bufon, Ferluga
-- Progetto elettronica 2 FPGA
-- Termometro visualizzato su VGA
----------------------------------------------------------------------------------

--Divisore in base 2 creato dalla Xilinx

-------------------------------------
-- Define datapath width
-------------------------------------
package mypackage is
	constant NBITS :INTEGER := 7;   --8;
	constant MBITS :INTEGER := 4;   --6;
end mypackage;

---------------------------------------------------------------
-- RESTORING Division Algorithm for natural operands
-- An NBITS natural divided by an MBITS natural
-- The resulting quotient is also naturals
-- Quotient Q of NBITS, and remainder R of MBITS
---------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.mypackage.all;

entity div_rest_nat is
    port (
        A: in STD_LOGIC_VECTOR (NBITS-1 downto 0);
        B: in STD_LOGIC_VECTOR (MBITS-1 downto 0);
        Q: out STD_LOGIC_VECTOR (NBITS-1 downto 0);
		  R: out STD_LOGIC_VECTOR (MBITS-1 downto 0)
     );
end div_rest_nat;

architecture div_arch of div_rest_nat is

component restoring_cell is
    port (
        a: in STD_LOGIC_VECTOR (MBITS downto 0);
        b: in STD_LOGIC_VECTOR (MBITS-1 downto 0);
  		  q: out STD_LOGIC;
		  r: out STD_LOGIC_VECTOR (MBITS downto 0)
     );
end component;

type conections is array (0 to NBITS-1) of STD_LOGIC_VECTOR (MBITS downto 0);
Signal wires_in, wires_out: conections;
Signal zeros: STD_LOGIC_VECTOR (MBITS-1 downto 0);

begin

 zeros <= (others => '0'); 
 wires_in(0) <= zeros & A(NBITS-1); 	 

 divisor: for i in 0 to NBITS-1 generate
    rest_cell: restoring_cell port map (a => wires_in(i),
  			 b => B, 
  		    q => Q(NBITS-I-1),
  			 r => wires_out(i));

 end generate;

 wires_conections: for i in 0 to NBITS-2 generate
        wires_in(i+1) <= wires_out(i)(MBITS-1 downto 0) & A(NBITS-i-2);			 
 end generate;

  R <= wires_out(NBITS-1)(MBITS-1 downto 0);

end div_arch;

---------------------------------------------------------
-- restoring cell
-- division step for restoring base-2 division algorithm
---------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.mypackage.all;

entity restoring_cell is
    port (
        a: in STD_LOGIC_VECTOR (MBITS downto 0);
        b: in STD_LOGIC_VECTOR (MBITS-1 downto 0);
  		  q: out STD_LOGIC;
		  r: out STD_LOGIC_VECTOR (MBITS downto 0)
     );
end restoring_cell;

architecture cel_arch of restoring_cell is

signal subst: STD_LOGIC_VECTOR (MBITS downto 0);

begin

subst <= a - b;

multiplexer: process (a,b,subst)
begin
	  if subst(MBITS) = '1' then
	 	 r <= a;
	  else
		 r <= subst;
	  end if; 
end process;

q <= not subst(MBITS);

end cel_arch;