contatore26bit.vhd

来自「simple thermometr in vhdl」· VHDL 代码 · 共 29 行

-- Progetto Elettronica 2 FPGA (2007) - Marco Mucchino & Giovanni Schiavon
-- Complemento a 2


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity contatore26bit is
    Port ( clock : in  STD_LOGIC;
	        reset : in std_logic;
           cont : inout  STD_LOGIC_VECTOR (25 downto 0));
end contatore26bit;

architecture Behavioral of contatore26bit is

begin

process (clock, reset) 
   begin
   if reset='1' then 
      cont <= "00000000000000000000000000";
   elsif clock='1' and clock'event then
      cont <= cont + 1;
   end if;
end process;

end Behavioral;