meno.vhd

来自「simple thermometr in vhdl」· VHDL 代码 · 共 43 行

----------------------------------------------------------------------------------
-- Bufon, Ferluga
-- Progetto elettronica 2 FPGA
-- Termometro visualizzato su VGA
----------------------------------------------------------------------------------

-- Tabella del segno meno
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Dichiarazione variabili d'ingresso e di uscita:

entity meno is
    Port ( clk : in  STD_LOGIC;
           add_linea : in  STD_LOGIC_VECTOR (8 downto 0);
           D_OUT : out  STD_LOGIC_VECTOR (18 downto 0));
end meno;

architecture Behavioral of meno is

begin

process(clk,add_linea)
begin

if ( clk'event and clk ='1') then
   case add_linea is



when "011101110" => D_OUT <= "1111111111111111111";
when "011101111" => D_OUT <= "1111111111111111111";
when "011110000" => D_OUT <= "1111111111111111111";
when "011110001" => D_OUT <= "1111111111111111111";
     when others => D_OUT <= "0000000000000000000";
   end case;
end if;
end process;

end Behavioral;