punto.vhd

simple thermometr in vhdl

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:37:02 11/20/2007 
-- Design Name: 
-- Module Name:    ena - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity punto is
    Port ( clk : in  STD_LOGIC;
           add_linea : in  STD_LOGIC_VECTOR (8 downto 0);
           D_OUT : out  STD_LOGIC_VECTOR (7 downto 0));
end punto;

architecture Behavioral of punto is

begin

process(clk,add_linea)
begin

if ( clk'event and clk ='1') then
   case add_linea is



when "100000001" => D_OUT <= "00111100";
when "100000010" => D_OUT <= "01111110";
when "100000011" => D_OUT <= "11111111";
when "100000100" => D_OUT <= "11111111";
when "100000101" => D_OUT <= "11111111";
when "100000110" => D_OUT <= "11111111";
when "100000111" => D_OUT <= "01111110";
when "100001000" => D_OUT <= "00111100";



	 when others => D_OUT <= "00000000";
   end case;
end if;
end process;

end Behavioral;