tre.vhd

simple thermometr in vhdl

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:48:09 11/20/2007 
-- Design Name: 
-- Module Name:    tri - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tri is
    Port ( clk : in  STD_LOGIC;
           add_linea : in  STD_LOGIC_VECTOR (8 downto 0);
           D_OUT : out  STD_LOGIC_VECTOR (26 downto 0));
end tri;

architecture Behavioral of tri is

begin
process(clk,add_linea)
begin

if ( clk'event and clk ='1') then
   case add_linea is

when "011011000" => D_OUT <= "000000000111111111100000000";
when "011011001" => D_OUT <= "000000111111111111111100000";
when "011011010" => D_OUT <= "000001111111111111111110000";
when "011011011" => D_OUT <= "000011111111111111111110000";
when "011011100" => D_OUT <= "000111111000001111111111000";
when "011011101" => D_OUT <= "000111000000000001111111000";
when "011011110" => D_OUT <= "001110000000000000111111100";
when "011011111" => D_OUT <= "001100000000000000011111100";
when "011100000" => D_OUT <= "001000000000000000011111100";
when "011100001" => D_OUT <= "000000000000000000001111100";
when "011100010" => D_OUT <= "000000000000000000001111100";
when "011100011" => D_OUT <= "000000000000000000001111100";
when "011100100" => D_OUT <= "000000000000000000001111000";
when "011100101" => D_OUT <= "000000000000000000001111000";
when "011100110" => D_OUT <= "000000000000000000011110000";
when "011100111" => D_OUT <= "000000000000000000011100000";
when "011101000" => D_OUT <= "000000000000000000111000000";
when "011101001" => D_OUT <= "000000000000000000110000000";
when "011101010" => D_OUT <= "000000000000000001100000000";
when "011101011" => D_OUT <= "000000000000000011000000000";
when "011101100" => D_OUT <= "000000000000000111110000000";
when "011101101" => D_OUT <= "000000000000011111111100000";
when "011101110" => D_OUT <= "000000000011111111111110000";
when "011101111" => D_OUT <= "000000001111111111111111000";
when "011110000" => D_OUT <= "000000000000011111111111100";
when "011110001" => D_OUT <= "000000000000000011111111100";
when "011110010" => D_OUT <= "000000000000000001111111110";
when "011110011" => D_OUT <= "000000000000000000011111110";
when "011110100" => D_OUT <= "000000000000000000001111110";
when "011110101" => D_OUT <= "000000000000000000001111111";
when "011110110" => D_OUT <= "000000000000000000000111111";
when "011110111" => D_OUT <= "000000000000000000000111111";
when "011111000" => D_OUT <= "000000000000000000000011111";
when "011111001" => D_OUT <= "000000000000000000000011111";
when "011111010" => D_OUT <= "000000000000000000000011111";
when "011111011" => D_OUT <= "000000000000000000000011110";
when "011111100" => D_OUT <= "000000000000000000000011110";
when "011111101" => D_OUT <= "000000000000000000000011110";
when "011111110" => D_OUT <= "000000000000000000000011100";
when "011111111" => D_OUT <= "000000000000000000000111100";
when "100000000" => D_OUT <= "000000000000000000000111000";
when "100000001" => D_OUT <= "000000000000000000000111000";
when "100000010" => D_OUT <= "011100000000000000001110000";
when "100000011" => D_OUT <= "111111000000000000011100000";
when "100000100" => D_OUT <= "111111110000000000111000000";
when "100000101" => D_OUT <= "111111111100000011110000000";
when "100000110" => D_OUT <= "011111111111111111100000000";
when "100000111" => D_OUT <= "001111111111111110000000000";
when "100001000" => D_OUT <= "000001111111110000000000000";



	 when others => D_OUT <= "000000000000000000000000000";
   end case;
end if;
end process;

end Behavioral;