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📄 otto.vhd

📁 simple thermometr in vhdl
💻 VHD
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------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date:    22:58:25 11/20/2007 -- Design Name: -- Module Name:    osem - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity osem is    Port ( clk : in  STD_LOGIC;           add_linea : in  STD_LOGIC_VECTOR (8 downto 0);           D_OUT : out  STD_LOGIC_VECTOR (27 downto 0));end osem;architecture Behavioral of osem isbeginprocess(clk,add_linea)beginif ( clk'event and clk ='1') then   case add_linea iswhen "011011000" => D_OUT <= "0000000001111111111100000000";when "011011001" => D_OUT <= "0000001111111111111111100000";when "011011010" => D_OUT <= "0000011111100000011111110000";when "011011011" => D_OUT <= "0000111110000000000111111000";when "011011100" => D_OUT <= "0001111110000000000111111100";when "011011101" => D_OUT <= "0011111110000000000111111100";when "011011110" => D_OUT <= "0011111100000000000011111110";when "011011111" => D_OUT <= "0111111100000000000011111110";when "011100000" => D_OUT <= "0111111100000000000011111110";when "011100001" => D_OUT <= "0111111100000000000011111110";when "011100010" => D_OUT <= "0111111100000000000011111110";when "011100011" => D_OUT <= "0111111110000000000011111100";when "011100100" => D_OUT <= "0111111110000000000111111100";when "011100101" => D_OUT <= "0111111111000000000111111000";when "011100110" => D_OUT <= "0011111111000000000111111000";when "011100111" => D_OUT <= "0011111111100000001111110000";when "011101000" => D_OUT <= "0001111111110000001111100000";when "011101001" => D_OUT <= "0001111111111000011111000000";when "011101010" => D_OUT <= "0000111111111100011110000000";when "011101011" => D_OUT <= "0000011111111110111100000000";when "011101100" => D_OUT <= "0000001111111111110000000000";when "011101101" => D_OUT <= "0000000111111111100000000000";when "011101110" => D_OUT <= "0000000011111111110000000000";when "011101111" => D_OUT <= "0000000001111111111100000000";when "011110000" => D_OUT <= "0000000011111111111110000000";when "011110001" => D_OUT <= "0000000111101111111111000000";when "011110010" => D_OUT <= "0000001111000111111111100000";when "011110011" => D_OUT <= "0000011110000011111111110000";when "011110100" => D_OUT <= "0000111110000001111111111000";when "011110101" => D_OUT <= "0001111110000000111111111100";when "011110110" => D_OUT <= "0011111100000000011111111100";when "011110111" => D_OUT <= "0011111100000000001111111110";when "011111000" => D_OUT <= "0111111100000000001111111110";when "011111001" => D_OUT <= "0111111000000000000111111111";when "011111010" => D_OUT <= "1111111000000000000011111111";when "011111011" => D_OUT <= "1111111000000000000011111111";when "011111100" => D_OUT <= "1111111000000000000001111111";when "011111101" => D_OUT <= "1111111000000000000001111111";when "011111110" => D_OUT <= "1111111000000000000001111111";when "011111111" => D_OUT <= "1111111000000000000001111111";when "100000000" => D_OUT <= "0111111000000000000001111110";when "100000001" => D_OUT <= "0111111100000000000001111110";when "100000010" => D_OUT <= "0011111100000000000001111100";when "100000011" => D_OUT <= "0011111110000000000011111100";when "100000100" => D_OUT <= "0001111110000000000011111000";when "100000101" => D_OUT <= "0000111111000000000111110000";when "100000110" => D_OUT <= "0000011111110000011111000000";when "100000111" => D_OUT <= "0000000111111111111110000000";when "100001000" => D_OUT <= "0000000001111111111000000000";	 when others => D_OUT <= "0000000000000000000000000000";   end case;end if;end process;end Behavioral;

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