selettore.vhd

simple thermometr in vhdl

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:23:42 11/20/2007 
-- Design Name: 
-- Module Name:    selettor - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity selettor is
    Port ( ena_in : in  STD_LOGIC_VECTOR (18 downto 0);
           dva_in : in  STD_LOGIC_VECTOR (29 downto 0);
           tri_in : in  STD_LOGIC_VECTOR (26 downto 0);
           stiri_in : in  STD_LOGIC_VECTOR (29 downto 0);
           pet_in : in  STD_LOGIC_VECTOR (26 downto 0);
           sest_in : in  STD_LOGIC_VECTOR (29 downto 0);
           sedem_in : in  STD_LOGIC_VECTOR (29 downto 0);
           osem_in : in  STD_LOGIC_VECTOR (27 downto 0);
           devet_in : in  STD_LOGIC_VECTOR (29 downto 0);
           nic_in : in  STD_LOGIC_VECTOR (29 downto 0);
			  meno_in : in  STD_LOGIC_VECTOR (18 downto 0);
			  punto_in : in  STD_LOGIC_VECTOR (7 downto 0);
			  gradi_in : in  STD_LOGIC_VECTOR (29 downto 0);
           st_out : out  STD_LOGIC_VECTOR (29 downto 0);
			  clk : in STD_LOGIC;
           stevilka : in  STD_LOGIC_VECTOR (3 downto 0));
end selettor;

architecture Behavioral of selettor is

begin

process(clk,stevilka)
begin
 if ( clk'event and clk ='1') then 
   case stevilka is
	
	when "0000" => st_out <= nic_in;
	when "0001" => st_out <= "000000" & ena_in & "00000";
	when "0010" => st_out <= dva_in;
	when "0011" => st_out <= "00" & tri_in & "0";
	when "0100" => st_out <= stiri_in;
	when "0101" => st_out <= "00" & pet_in & "0";
	when "0110" => st_out <= sest_in;
	when "0111" => st_out <= sedem_in;
	when "1000" => st_out <= "0" & osem_in & "0";
	when "1001" => st_out <= devet_in;
	when "1010" => st_out <= "00" & meno_in & "000000000";
	when "1011" => st_out <= punto_in & "0000000000000000000000";
	when "1100" => st_out <= gradi_in;
	when "1111" => st_out <= "000000000000000000000000000000";
	
		 when others => NULL;
   end case;
end if;
end process;	
end Behavioral;