swap.vhd

simple thermometr in vhdl

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:04:19 11/22/2007 
-- Design Name: 
-- Module Name:    swap - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity swap is
    Port ( ingr : in  STD_LOGIC_VECTOR (29 downto 0);
           usci : out  STD_LOGIC_VECTOR (29 downto 0));
end swap;

architecture Behavioral of swap is

begin
usci(0) <= ingr(29);
usci(1) <= ingr(28);
usci(2) <= ingr(27);
usci(3) <= ingr(26);
usci(4) <= ingr(25);
usci(5) <= ingr(24);
usci(6) <= ingr(23);
usci(7) <= ingr(22);
usci(8) <= ingr(21);
usci(9) <= ingr(20);
usci(10) <= ingr(19);
usci(11) <= ingr(18);
usci(12) <= ingr(17);
usci(13) <= ingr(16);
usci(14) <= ingr(15);
usci(15) <= ingr(14);
usci(16) <= ingr(13);
usci(17) <= ingr(12);
usci(18) <= ingr(11);
usci(19) <= ingr(10);
usci(20) <= ingr(9);
usci(21) <= ingr(8);
usci(22) <= ingr(7);
usci(23) <= ingr(6);
usci(24) <= ingr(5);
usci(25) <= ingr(4);
usci(26) <= ingr(3);
usci(27) <= ingr(2);
usci(28) <= ingr(1);
usci(29) <= ingr(0);



end Behavioral;