sincronismo.vhd

simple thermometr in vhdl

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-- Bufon, Ferluga
-- Progetto elettronica 2 FPGA
-- Termometro visualizzato su VGA
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--Blocco che sincronizza l'uscita con il reset

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Dichiarazione variabili d'ingresso e di uscita:

entity Sincronismo is
port(clk : in std_logic;
	cfr1_in :in std_logic_vector (3 downto 0);
	cfr2_in :in std_logic_vector (3 downto 0);
	cfr3_in :in std_logic_vector (3 downto 0);
	cfr1_out :out std_logic_vector (3 downto 0);
	cfr2_out :out std_logic_vector (3 downto 0);
	cfr3_out :out std_logic_vector (3 downto 0));
end Sincronismo;

architecture Behavioral of Sincronismo is

begin
  process(clk)
  begin
  if(clk='1' and clk' event)then
  cfr1_out <= cfr1_in;
  cfr2_out <= cfr2_in;
  cfr3_out <= cfr3_in;
  end if;
  end process;
end Behavioral;