caratteri.vhf

simple thermometr in vhdl

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
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--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 9.2i
--  \   \         Application : sch2vhdl
--  /   /         Filename : Caratteri.vhf
-- /___/   /\     Timestamp : 12/02/2007 20:41:05
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: C:\Xilinx92i\bin\nt\sch2vhdl.exe -intstyle ise -family spartan2 -flat -suppress -w "C:/Documents and Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA/VGAterm/caratteri.sch" Caratteri.vhf
--Design Name: caratteri
--Device: spartan2
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesis and simulted, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity caratteri is
   port ( cifra    : in    std_logic_vector (3 downto 0); 
          clk      : in    std_logic; 
          line_add : in    std_logic_vector (8 downto 0); 
          dato     : out   std_logic_vector (33 downto 0));
end caratteri;

architecture BEHAVIORAL of caratteri is
   signal XLXN_1   : std_logic_vector (18 downto 0);
   signal XLXN_2   : std_logic_vector (29 downto 0);
   signal XLXN_3   : std_logic_vector (26 downto 0);
   signal XLXN_4   : std_logic_vector (29 downto 0);
   signal XLXN_5   : std_logic_vector (26 downto 0);
   signal XLXN_6   : std_logic_vector (29 downto 0);
   signal XLXN_7   : std_logic_vector (29 downto 0);
   signal XLXN_8   : std_logic_vector (27 downto 0);
   signal XLXN_9   : std_logic_vector (29 downto 0);
   signal XLXN_19  : std_logic_vector (29 downto 0);
   signal XLXN_20  : std_logic_vector (18 downto 0);
   signal XLXN_22  : std_logic_vector (29 downto 0);
   signal XLXN_23  : std_logic_vector (7 downto 0);
   component devet
      port ( clk       : in    std_logic; 
             add_linea : in    std_logic_vector (8 downto 0); 
             D_OUT     : out   std_logic_vector (29 downto 0));
   end component;
   
   component dva
      port ( clk       : in    std_logic; 
             add_linea : in    std_logic_vector (8 downto 0); 
             D_OUT     : out   std_logic_vector (29 downto 0));
   end component;
   
   component ena
      port ( clk       : in    std_logic; 
             add_linea : in    std_logic_vector (8 downto 0); 
             D_OUT     : out   std_logic_vector (18 downto 0));
   end component;
   
   component tri
      port ( clk       : in    std_logic; 
             add_linea : in    std_logic_vector (8 downto 0); 
             D_OUT     : out   std_logic_vector (26 downto 0));
   end component;
   
   component stiri
      port ( clk       : in    std_logic; 
             add_linea : in    std_logic_vector (8 downto 0); 
             D_OUT     : out   std_logic_vector (29 downto 0));
   end component;
   
   component pet
      port ( clk       : in    std_logic; 
             add_linea : in    std_logic_vector (8 downto 0); 
             D_OUT     : out   std_logic_vector (26 downto 0));
   end component;
   
   component sest
      port ( clk       : in    std_logic; 
             add_linea : in    std_logic_vector (8 downto 0); 
             D_OUT     : out   std_logic_vector (29 downto 0));
   end component;
   
   component sedem
      port ( clk       : in    std_logic; 
             add_linea : in    std_logic_vector (8 downto 0); 
             D_OUT     : out   std_logic_vector (29 downto 0));
   end component;
   
   component osem
      port ( clk       : in    std_logic; 
             add_linea : in    std_logic_vector (8 downto 0); 
             D_OUT     : out   std_logic_vector (27 downto 0));
   end component;
   
   component nic
      port ( clk       : in    std_logic; 
             add_linea : in    std_logic_vector (8 downto 0); 
             D_OUT     : out   std_logic_vector (29 downto 0));
   end component;
   
   component selettor
      port ( clk      : in    std_logic; 
             ena_in   : in    std_logic_vector (18 downto 0); 
             dva_in   : in    std_logic_vector (29 downto 0); 
             tri_in   : in    std_logic_vector (26 downto 0); 
             stiri_in : in    std_logic_vector (29 downto 0); 
             pet_in   : in    std_logic_vector (26 downto 0); 
             sest_in  : in    std_logic_vector (29 downto 0); 
             sedem_in : in    std_logic_vector (29 downto 0); 
             osem_in  : in    std_logic_vector (27 downto 0); 
             devet_in : in    std_logic_vector (29 downto 0); 
             nic_in   : in    std_logic_vector (29 downto 0); 
             meno_in  : in    std_logic_vector (18 downto 0); 
             punto_in : in    std_logic_vector (7 downto 0); 
             gradi_in : in    std_logic_vector (29 downto 0); 
             stevilka : in    std_logic_vector (3 downto 0); 
             st_out   : out   std_logic_vector (33 downto 0));
   end component;
   
   component meno
      port ( clk       : in    std_logic; 
             add_linea : in    std_logic_vector (8 downto 0); 
             D_OUT     : out   std_logic_vector (18 downto 0));
   end component;
   
   component punto
      port ( clk       : in    std_logic; 
             add_linea : in    std_logic_vector (8 downto 0); 
             D_OUT     : out   std_logic_vector (7 downto 0));
   end component;
   
   component gradi
      port ( clk       : in    std_logic; 
             add_linea : in    std_logic_vector (8 downto 0); 
             D_OUT     : out   std_logic_vector (29 downto 0));
   end component;
   
begin
   XLXI_1 : devet
      port map (add_linea(8 downto 0)=>line_add(8 downto 0),
                clk=>clk,
                D_OUT(29 downto 0)=>XLXN_9(29 downto 0));
   
   XLXI_2 : dva
      port map (add_linea(8 downto 0)=>line_add(8 downto 0),
                clk=>clk,
                D_OUT(29 downto 0)=>XLXN_2(29 downto 0));
   
   XLXI_3 : ena
      port map (add_linea(8 downto 0)=>line_add(8 downto 0),
                clk=>clk,
                D_OUT(18 downto 0)=>XLXN_1(18 downto 0));
   
   XLXI_4 : tri
      port map (add_linea(8 downto 0)=>line_add(8 downto 0),
                clk=>clk,
                D_OUT(26 downto 0)=>XLXN_3(26 downto 0));
   
   XLXI_5 : stiri
      port map (add_linea(8 downto 0)=>line_add(8 downto 0),
                clk=>clk,
                D_OUT(29 downto 0)=>XLXN_4(29 downto 0));
   
   XLXI_6 : pet
      port map (add_linea(8 downto 0)=>line_add(8 downto 0),
                clk=>clk,
                D_OUT(26 downto 0)=>XLXN_5(26 downto 0));
   
   XLXI_7 : sest
      port map (add_linea(8 downto 0)=>line_add(8 downto 0),
                clk=>clk,
                D_OUT(29 downto 0)=>XLXN_6(29 downto 0));
   
   XLXI_8 : sedem
      port map (add_linea(8 downto 0)=>line_add(8 downto 0),
                clk=>clk,
                D_OUT(29 downto 0)=>XLXN_7(29 downto 0));
   
   XLXI_9 : osem
      port map (add_linea(8 downto 0)=>line_add(8 downto 0),
                clk=>clk,
                D_OUT(27 downto 0)=>XLXN_8(27 downto 0));
   
   XLXI_10 : nic
      port map (add_linea(8 downto 0)=>line_add(8 downto 0),
                clk=>clk,
                D_OUT(29 downto 0)=>XLXN_19(29 downto 0));
   
   XLXI_11 : selettor
      port map (clk=>clk,
                devet_in(29 downto 0)=>XLXN_9(29 downto 0),
                dva_in(29 downto 0)=>XLXN_2(29 downto 0),
                ena_in(18 downto 0)=>XLXN_1(18 downto 0),
                gradi_in(29 downto 0)=>XLXN_22(29 downto 0),
                meno_in(18 downto 0)=>XLXN_20(18 downto 0),
                nic_in(29 downto 0)=>XLXN_19(29 downto 0),
                osem_in(27 downto 0)=>XLXN_8(27 downto 0),
                pet_in(26 downto 0)=>XLXN_5(26 downto 0),
                punto_in(7 downto 0)=>XLXN_23(7 downto 0),
                sedem_in(29 downto 0)=>XLXN_7(29 downto 0),
                sest_in(29 downto 0)=>XLXN_6(29 downto 0),
                stevilka(3 downto 0)=>cifra(3 downto 0),
                stiri_in(29 downto 0)=>XLXN_4(29 downto 0),
                tri_in(26 downto 0)=>XLXN_3(26 downto 0),
                st_out(33 downto 0)=>dato(33 downto 0));
   
   XLXI_12 : meno
      port map (add_linea(8 downto 0)=>line_add(8 downto 0),
                clk=>clk,
                D_OUT(18 downto 0)=>XLXN_20(18 downto 0));
   
   XLXI_13 : punto
      port map (add_linea(8 downto 0)=>line_add(8 downto 0),
                clk=>clk,
                D_OUT(7 downto 0)=>XLXN_23(7 downto 0));
   
   XLXI_14 : gradi
      port map (add_linea(8 downto 0)=>line_add(8 downto 0),
                clk=>clk,
                D_OUT(29 downto 0)=>XLXN_22(29 downto 0));
   
end BEHAVIORAL;