generale.mrp

simple thermometr in vhdl

Release 6.2.03i Map G.31a
Xilinx Mapping Report File for Design 'generale'

Design Information
------------------
Command Line   : C:/Xilinx/bin/nt/map.exe -intstyle ise -p xc2s50-tq144-5 -cm
area -pr b -k 4 -c 100 -tx off -o generale_map.ncd generale.ngd generale.pcf 
Target Device  : x2s50
Target Package : tq144
Target Speed   : -5
Mapper Version : spartan2 -- $Revision: 1.16.8.1 $
Mapped Date    : Thu Nov 29 19:20:29 2007

Design Summary
--------------
Number of errors:      1
Number of warnings:    5
Logic Utilization:
  Total Number Slice Registers:     507 out of  1,536   33%
    Number used as Flip Flops:                    490
    Number used as Latches:                        17
  Number of 4 input LUTs:         1,474 out of  1,536   95%
Logic Distribution:
    Number of occupied Slices:                         775 out of    768  100%
(OVERMAPPED)
    Number of Slices containing only related logic:    684 out of    775   88%
    Number of Slices containing unrelated logic:        91 out of    775   11%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        1,537 out of  1,536  100% (OVERMAPPED)
      Number used as logic:                     1,474
      Number used as a route-thru:                 61
      Number used as Shift registers:               2
   Number of bonded IOBs:             9 out of     92    9%
      IOB Flip Flops:                               3
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  14,752
Additional JTAG gate count for IOBs:  480
Peak Memory Usage:  66 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Additional Device Resource Counts

Section 1 - Errors
------------------
ERROR:Pack:18 - The design is too large for the given device and package. 
   Please check the Design Summary section to see which resource requirement for
   your design exceeds the resources available in the device.
   

If the slice count exceeds device resources you might try to disable
   register ordering (-r).  Also if your design contains AREA_GROUPs, you may be
   able to improve density by adding COMPRESSION to your AREA_GROUPs if you
   haven't done so already.
   

NOTE: An NCD file will still be generated to allow you to examine the mapped
   design.  This file is intended for evaluation use only, and will not process
   successfully through PAR.
   

This mapped NCD file can be used to evaluate how the design's logic has been
   mapped into FPGA logic resources.  It can also be used to analyze
   preliminary, logic-level (pre-route) timing with one of the Xilinx static
   timing analysis tools (TRCE or Timing Analyzer).

Section 2 - Warnings
--------------------
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net XLXI_15_Q_1 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net XLXI_15_Q_2 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net clk is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net XLXI_15_Q_3 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net
   XLXI_24_XLXI_4_ow_master_i__n0044 is sourced by a combinatorial pin. This is
   not good design practice. Use the CE pin to control the loading of data into
   the flip-flop.

Section 3 - Informational
-------------------------
INFO:LIT:95 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.
INFO:MapLib:562 - No environment variables are currently set.

Section 4 - Removed Logic Summary
---------------------------------
   9 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
VCC 		XLXI_16
GND 		XLXI_17
LUT1 		XLXI_23_XLXI_1_Mcompar__n0009_inst_inv_0_rt
LUT1 		XLXI_23_XLXI_1_Mcompar__n0009_inst_inv_0_rt1
LUT1 		XLXI_23_XLXI_1_Mcompar__n0009_inst_inv_0_rt2
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clk88                              | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       |
| hs                                 | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| onewire                            | IOB     | BIDIR     | LVTTL       | 12       | SLOW | INFF     | PULLUP   | IFD   |
| rgb<0>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rgb<1>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rgb<2>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rgb<3>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rgb<4>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rgb<5>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| vs                                 | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------
XLXI_15_0                               

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

Section 13 - Additional Device Resource Counts
----------------------------------------------
Number of JTAG Gates for IOBs = 10
Number of Equivalent Gates for Design = 14,752
Number of RPM Macros = 0
Number of Hard Macros = 0
PCI IOBs = 0
PCI LOGICs = 0
CAPTUREs = 0
BSCANs = 0
STARTUPs = 0
DLLs = 0
GCLKIOBs = 1
GCLKs = 1
Block RAMs = 0
TBUFs = 0
Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 192
IOB Latches not driven by LUTs = 0
IOB Latches = 0
IOB Flip Flops not driven by LUTs = 3
IOB Flip Flops = 3
Unbonded IOBs = 0
Bonded IOBs = 9
Shift Registers = 2
Static Shift Registers = 2
Dynamic Shift Registers = 0
16x1 ROMs = 0
16x1 RAMs = 0
32x1 RAMs = 0
Dual Port RAMs = 0
MULTANDs = 0
MUXF5s + MUXF6s = 44
4 input LUTs used as Route-Thrus = 61
4 input LUTs = 1474
Slice Latches not driven by LUTs = 9
Slice Latches = 17
Slice Flip Flops not driven by LUTs = 180
Slice Flip Flops = 490
Slices = 775
Number of LUT signals with 4 loads = 25
Number of LUT signals with 3 loads = 58
Number of LUT signals with 2 loads = 129
Number of LUT signals with 1 load = 1164
NGM Average fanout of LUT = 2.13
NGM Maximum fanout of LUT = 94
NGM Average fanin for LUT = 3.4362
Number of LUT symbols = 1474
Number of IPAD symbols = 1
Number of IBUF symbols = 1
Number of BIPAD symbols = 1