estrai_cifre.vhf

simple thermometr in vhdl

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-- Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
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--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 9.2i
--  \   \         Application : sch2vhdl
--  /   /         Filename : estrai_cifre.vhf
-- /___/   /\     Timestamp : 12/02/2007 20:41:06
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: C:\Xilinx92i\bin\nt\sch2vhdl.exe -intstyle ise -family spartan2 -flat -suppress -w "C:/Documents and Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA/VGAterm/estrai_cifre.sch" estrai_cifre.vhf
--Design Name: estrai_cifre
--Device: spartan2
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesis and simulted, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity estrai_cifre is
   port ( temp_int : in    std_logic_vector (6 downto 0); 
          seq1     : out   std_logic_vector (3 downto 0); 
          seq2     : out   std_logic_vector (3 downto 0); 
          seq3     : out   std_logic_vector (3 downto 0));
end estrai_cifre;

architecture BEHAVIORAL of estrai_cifre is
   signal XLXN_3   : std_logic_vector (3 downto 0);
   signal XLXN_5   : std_logic_vector (6 downto 0);
   signal XLXN_6   : std_logic_vector (6 downto 0);
   component costante_dieci
      port ( dieci : out   std_logic_vector (3 downto 0));
   end component;
   
   component div_rest_nat
      port ( A : in    std_logic_vector (6 downto 0); 
             B : in    std_logic_vector (3 downto 0); 
             Q : out   std_logic_vector (6 downto 0); 
             R : out   std_logic_vector (3 downto 0));
   end component;
   
begin
   XLXI_1 : costante_dieci
      port map (dieci(3 downto 0)=>XLXN_3(3 downto 0));
   
   XLXI_2 : div_rest_nat
      port map (A(6 downto 0)=>temp_int(6 downto 0),
                B(3 downto 0)=>XLXN_3(3 downto 0),
                Q(6 downto 0)=>XLXN_5(6 downto 0),
                R(3 downto 0)=>seq3(3 downto 0));
   
   XLXI_3 : div_rest_nat
      port map (A(6 downto 0)=>XLXN_5(6 downto 0),
                B(3 downto 0)=>XLXN_3(3 downto 0),
                Q(6 downto 0)=>XLXN_6(6 downto 0),
                R(3 downto 0)=>seq2(3 downto 0));
   
   XLXI_4 : div_rest_nat
      port map (A(6 downto 0)=>XLXN_6(6 downto 0),
                B(3 downto 0)=>XLXN_3(3 downto 0),
                Q=>open,
                R(3 downto 0)=>seq1(3 downto 0));
   
end BEHAVIORAL;