📄 onewire_master.vhd
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------------------------------------------------------------------------
--
-- If we employ CRC check circuit,
--
crcgen : if CheckCRC = true generate
crcreg_i: CRCReg
generic map (
width => 8,
feedback1 => 4,
feedback2 => 5)
port map (
clk => clk_1MHz, -- for each bit, use faster clock
reset => reset, -- asynchronous reset !
d => din,
en => crcreg_en,
q => crcvalue_i);
-- This enable signal is generated for each data bit when we
-- receive the crc data from the one-wire device. It's 1us pulse.
-- use sr2_q(7) here to exclude the situation when we receive
-- the crc value from the one-wire device.
crcreg_en <= databit_valid and (not sr2_q(7));
-- Assert crcok signal when the last byte of data (crc value) is
-- received and it matches the caculated crc value from the CRCReg
crcokreg: process (clk_1MHz, reset)
begin
if reset = '1' then -- need asynchonous reset
crcok_i <= '0';
elsif clk_1MHz'event and clk_1MHz = '1' then
if sr2_q(7) = '1' and databyte_valid = '1' and data_i = crcvalue_i then
crcok_i <= '1';
end if;
end if;
end process crcokreg;
end generate crcgen;
--
-- If we do not use CRC check circuit,
--
nocrcgen : if CheckCRC = false generate
-- Assert crcok when the all the data has been received
crcokreg: process (clk_1MHz, reset)
begin
if reset = '1' then -- need asynchonous reset
crcok_i <= '0';
elsif clk_1MHz'event and clk_1MHz = '1' then
if sr2_q(7) = '1' and databyte_valid = '1'then
crcok_i <= '1';
end if;
end if;
end process crcokreg;
end generate nocrcgen;
----------------------------------------------------------------------------
-- The Presence Pulse Register
----------------------------------------------------------------------------
ppreg: process(clk_50KHz, reset)
begin
if reset = '1' then
din_pp <= '1';
elsif clk_50KHz'event and clk_50KHz = '1' then
if sr2_q(0) = '1' and thisState = RX_PRE_PLS then
din_pp <= din;
end if;
end if;
end process ppreg;
----------------------------------------------------------------------------
-- The FSM register
----------------------------------------------------------------------------
fsmr: process (clk_50KHz, reset)
begin -- process fsmr
if reset = '1' then -- asynchronous reset !
thisState <= INIT;
elsif clk_50KHz'event and clk_50KHz = '1' then
thisState <= nextState;
end if;
end process fsmr;
-- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% MODIFICA %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
----------------------------------------------------------------------------
-- Registro avvenuta conversione temperatura
----------------------------------------------------------------------------
ctreg: process(thisState, reset)
begin
if thisState = TX_CONVERTT_CMD then
conv_ok <= '1';
elsif (thisState = TX_SCR_CDM or reset = '1') then
conv_ok <= '0';
end if;
end process ctreg;
-- %%%%%%%%%%%%%%%%%%%%%%%%%%% FINE MODIFICA %%%%%%%%%%%%%%%%%%%%%%%%%%%
------------------------------------------------------------------------
-- State Mux
-- Combinational Logic for the state machine.
--
-- Any action in this state mux is synchronized with the 20 us clock
-- and a few of them are synchronized with the 1us clock.
--
-- The transition of the state will take effect on next
-- rising edge of the clock.
------------------------------------------------------------------------
statemux: process (thisState, din_pp, din, sr1_q, sr2_q,
ts_60_to_80us, ts_0_to_10us, ts_0_to_1us, ts_14_to_15us,
tx_cmd_bit, crcok_i)
begin
-- Default values assigned to these signals
-- Any signal without an assignment in the combinational logic
-- will use these default values.
nextState <= thisState; -- stay at current state by default
sr1_reset <= '1'; -- hold sr1 at reset by default
sr1_en <= '0';
sr2_reset <= '1'; -- hold sr2 at reset by default
sr2_en <= '0';
dout <= '1'; -- data output to the one-wire bus
d_ctrl <= '1'; -- read mode on the one-wire bus by default
databyte_valid <= '0'; -- data enable signal for a byte of data
databit_valid <= '0'; -- data valid strobe for a bit of data
jc1_reset <= '0'; -- hold jc1 at reset by default
-- Case statement as a Mux
case thisState is
when INIT => ---------------------------------------
-- Reset/Initialization state
---------------------------------------
-- The one-wire bus will be pulled up,
-- so that next state we can send a
-- Reset Pulse (active low) to the bus.
---------------------------------------
dout <= '1'; -- begin the operation by pulling up
-- one-wire bus to high
d_ctrl <= '0'; -- write to the one-wire bus
nextState <= TX_RST_PLS;
jc1_reset <= '1';
when TX_RST_PLS => ---------------------------------------
-- Transmit Reset Pulse state
---------------------------------------
-- In this state, the one-wire bus will
-- be pulled down (Tx "Reset Pulse") for
-- 480 us to reset the one-wire
-- device connected to the bus.
--
-- It enables FSM to move to next state
-- at 480 us. The transition of the state
-- will happend at 500 us.
--
-- Use JC1 and SR2 here to count for
-- longer time duration (0 ~ 480 us):
-----------------------------------------
-- Time JC1 SR2 SR2 SR2
-- elapse En Rst
-- (us) msb lsb
-----------------------------------------
-- 0 "00" '0' '0' "00000001"
-- 20 "01" '0' '0' "00000001"
-- 40 "11" '0' '0' "00000001"
-- 60 "10" '1' '0' "00000001"
-- 80 "00" '0' '0' "00000010"
-- 100 "01" '0' '0' "00000010"
-- 120 "11" '0' '0' "00000010"
-- 140 "10" '1' '0' "00000010"
-- 160 "00" '0' '0' "00000100"
-- 180 "01" '0' '0' "00000100"
-- ... ... ... ... ...
-- ... ... ... ... ...
-- 240 "00" '0' '0' "00001000"
-- ... ... ... ... ...
-- 320 "00" '0' '0' "00010000"
-- ... ... ... ... ...
-- 400 "00" '0' '0' "00100000"
-- ... ... ... ... ...
-- 480 "00" '0' '1' "01000000"
-- 500 "01" '0' '0' "00000001"
----------------------------------------
sr2_en <= ts_60_to_80us; -- enable sr2 to shift every 80 us,
-- transition will occur at next clock
-- cycle
if sr2_q(6) = '1' then -- count till 480 us has passed.
d_ctrl <= '1'; -- release one-wire bus by changing to
-- read mode
nextState <= RX_PRE_PLS; -- goes to next state
jc1_reset <= '1';
sr2_reset <= '1'; -- reset sr2 at 480us
else -- 0 ~ 480 us
d_ctrl <= '0'; -- write data to one-wire bus
dout <= '0'; -- Tx "Reset Pulse" for 480us
sr2_reset <= '0'; -- use sr2 to count for longer
-- time duration (0 ~ 480 us),
end if;
when RX_PRE_PLS =>
---------------------------------------
-- Detect Presence Pulse state
---------------------------------------
-- In this state, it sample the data
-- on the one wire bus when the
-- "Presence Pulse" will occur.
-- The data will be latched at 0~80 us.
-- Then it waits till total 500us has
-- has passed, and moves to next state
-- or goes back to INIT state according
-- to the presence of the "Presence
-- Pulse"
--
-- Use JC1 and SR2 here to count for
-- longer time duration (0 ~ 480 us):
--
-- Note:"Presence Pulse" indicates
-- a Serial Number Device is on the bus
-- and it's ready to operate.
----------------------------------------
sr2_reset <= '0' ; -- use sr2 to count for longer
-- time duration (0 ~ 480 us),
sr2_en <= ts_60_to_80us; -- enable sr2 to shift every 80 us
if sr2_q(6) = '1' then -- 480us passed
d_ctrl <= '1'; -- remain read status on the bus
if din_pp ='0' and din = '1' then -- detect presence pulse
-- and pull up after the
-- presence pulse
nextState <= TX_SKIP_CMD;
jc1_reset <= '1';
else
nextState <= INIT;
end if;
else -- 0 ~ 480 us
d_ctrl <= '1'; -- use read mode on the one-wire bus
end if;
-- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% MODIFICA %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
--Modifica degli ststi presenti/Aggiunta degli stati necessari al progetto
when TX_SKIP_CMD => ---------------------------------------
-- Stato di trasmissione del comando "Skip ROM"
---------------------------------------
-- Si trasmette il comando di Skip ROM
-- utilizzando opportunamente lo sr1 per
-- trasmettere tutti gli 8 bit di comando.
-- Quando ci⌨️ 快捷键说明
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