onewire_master.vhd

simple thermometr in vhdl

                                  -- one bit of data into the register
  
  -- signals for byte register (ByteReg)
  signal bytereg_en : std_logic_vector(5 downto 0); -- enable signal to load
                                  -- one byte of data into the register
  
  -- several data valid signals
  signal databit_valid: std_logic;-- databit_valid signal generated from sr1
                                  -- (which identifies states), it's
                                  -- 1us pulse. It indicates
                                  -- the valid data received from the 
                                  -- Serial Number Device, excludes
                                  -- the Presence Pulse.
                                  

  signal databyte_valid: std_logic;
                                  -- valid signal for receiving a byte of
                                  -- the number data from the Serial Number
                                  -- Device.
                                  -- Include: family code, serial number
                                  -- and crc value. It's 1 us pulse.
  
  -- signals for CRC check circuit
  signal crcreg_en : std_logic;   -- enable one bit data loaded into
                                  -- the CRC Register.

  signal crcvalue_i: std_logic_vector (7 downto 0); -- The calculated
                                  -- CRC value from the CRC register
  

  -- some internal signals for internal wiring
  signal data_i  : std_logic_vector(7 downto 0); -- to data output
  signal crcok_i : std_logic;                 -- to crcok output

  -- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% MODIFICA %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
  --aggiunto segnale di notifica per avvenuta conversione
  
  signal conv_ok : std_logic;
 
  -- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% FINE MODIFICA %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
  
  
  -- some signals for wiring

  signal vcc : std_logic;

  signal gnd : std_logic;

  
begin

  -------------------------------------------------------------------
  -- internal wiring
  -------------------------------------------------------------------
  vcc     <= '1';

  gnd     <= '0';

  data    <= data_i;           -- a byte of number data to outside
  
  crcok   <= crcok_i;

  -------------------------------------------------------------------
  -- Register the data_valid signals
  -------------------------------------------------------------------
  regs: process (clk_1MHz, reset)
    begin
      if reset = '1' then
         data_valid <= '0';
      elsif clk_1MHz'event and clk_1MHz = '1' then
         data_valid <= databyte_valid; -- the data_valid output connects
                                       -- to the valid signal when
                                       -- getting a byte of data
      end if;
   end process regs;

  -------------------------------------------------------------------
  -- Clock generation
  -------------------------------------------------------------------
  clk_50KHz <= not jc2_q(9);   -- use the msb of JC2 to generate
                               -- 50KHz slow clock
                               -- use "not" here to generate rising
                               -- edge at proper position

                               
  -------------------------------------------------------------------
  -- Several time slot identification signals
  -------------------------------------------------------------------
  -- Suppose the beginning of each state is time 0.
  -- Use combination of JC1 and JC2, we can id any time slot during
  -- each state as small as 1 us.
  ts_60_to_80us <= jc1_q(1) and (not jc1_q(0));
  ts_0_to_10us  <= (not jc1_q(0)) and (not jc2_q(9));
  ts_0_to_1us   <= ts_0_to_10us and (not jc2_q(0)) ;
  ts_14_to_15us <= (not jc1_q(0)) and jc2_q(4) and (not jc2_q(3));  
  
  -------------------------------------------------------------------
  -- Command data bit to transmit (write) to the one wire bus
  -- Use SR1 to pick up each bit out of the Command data byte.
  -------------------------------------------------------------------
  -- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% MODIFICA %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
  --implementata la configurazione per l'invio dei registri di comando 
  
  tx_cmd_bit      <= SkipROMCmd(0) when (sr1_q(0) = '1' and thisState=TX_SKIP_CMD)
                else SkipROMCmd(1) when (sr1_q(1) = '1' and thisState=TX_SKIP_CMD)
                else SkipROMCmd(2) when (sr1_q(2) = '1' and thisState=TX_SKIP_CMD)
                else SkipROMCmd(3) when (sr1_q(3) = '1' and thisState=TX_SKIP_CMD)
                else SkipROMCmd(4) when (sr1_q(4) = '1' and thisState=TX_SKIP_CMD)
                else SkipROMCmd(5) when (sr1_q(5) = '1' and thisState=TX_SKIP_CMD)
                else SkipROMCmd(6) when (sr1_q(6) = '1' and thisState=TX_SKIP_CMD)
                else SkipROMCmd(7) when (sr1_q(7) = '1' and thisState=TX_SKIP_CMD)
					 else ConvertTCmd(0) when (sr1_q(0) = '1' and thisState=TX_CONVERTT_CMD)
                else ConvertTCmd(1) when (sr1_q(1) = '1' and thisState=TX_CONVERTT_CMD)
                else ConvertTCmd(2) when (sr1_q(2) = '1' and thisState=TX_CONVERTT_CMD)
                else ConvertTCmd(3) when (sr1_q(3) = '1' and thisState=TX_CONVERTT_CMD)
                else ConvertTCmd(4) when (sr1_q(4) = '1' and thisState=TX_CONVERTT_CMD)
                else ConvertTCmd(5) when (sr1_q(5) = '1' and thisState=TX_CONVERTT_CMD)
                else ConvertTCmd(6) when (sr1_q(6) = '1' and thisState=TX_CONVERTT_CMD)
                else ConvertTCmd(7) when (sr1_q(7) = '1' and thisState=TX_CONVERTT_CMD)
					 else ReadSCRCmd(0) when (sr1_q(0) = '1' and thisState=TX_SCR_CDM)
                else ReadSCRCmd(1) when (sr1_q(1) = '1' and thisState=TX_SCR_CDM)
                else ReadSCRCmd(2) when (sr1_q(2) = '1' and thisState=TX_SCR_CDM)
                else ReadSCRCmd(3) when (sr1_q(3) = '1' and thisState=TX_SCR_CDM)
                else ReadSCRCmd(4) when (sr1_q(4) = '1' and thisState=TX_SCR_CDM)
                else ReadSCRCmd(5) when (sr1_q(5) = '1' and thisState=TX_SCR_CDM)
                else ReadSCRCmd(6) when (sr1_q(6) = '1' and thisState=TX_SCR_CDM)
                else ReadSCRCmd(7) when (sr1_q(7) = '1' and thisState=TX_SCR_CDM)
                else '0';

  -- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% FINE MODIFICA %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
  
  -------------------------------------------------------------------
  -- Bidirectional iobuffer to control the direction of data flow on
  -- the one-wire bus
  -------------------------------------------------------------------  
   iobuf_i : iobuf
          port map (
            T  => d_ctrl, -- control signal to switch in/out
            IO => dq,     -- connect to bidirectional one-wire bus
            I  => dout,   -- data output to the bus
            O  => din);   -- data input from the bus


  -------------------------------------------------------------------
  -- Shift Register 1 
  -- Used to count 8 bits in a byte of data
  -------------------------------------------------------------------
   sr1: SHReg      
          generic map (
            circular => true,  -- 8 bits in a row and scroll over
            AsynReset=> false,
            width    => 8)
          port map (
              reset  => sr1_reset, -- synchronous reset
              clk    => clk_50KHz,
              en     => sr1_en,
              q      => sr1_q);
              
  -------------------------------------------------------------------
  -- Shift Register 2  
  -- Used to count 8 bytes stored in the Serial Number Device
  -------------------------------------------------------------------
   sr2: SHReg      
          generic map (
            circular => false,
            AsynReset=> false,
            width    => 8)
          port map (
            reset    => sr2_reset, -- synchronous reset
            clk      => clk_50KHz,
            en       => sr2_en,
            q        => sr2_q);

  -------------------------------------------------------------------
  -- Johnson Counter 1  
  -- This Johnson counter is used to deal with the time slots.
  -- It chops one state into small time slots.Each is 20 us long,
  -- total 4 slots. 
  -- The reason to use Johnson Counter is to save register bits.
  -- n bits of Johnson counter can count for 2n values.
  -- for the shift register, n bits can only count for n values
  -- In addition, Johnson counter is fast since only NOT gates
  -- are used in this counter.
  -- It's driven by the slow clock (20us) in this system.
  -------------------------------------------------------------------
   jcnt1: JCounter          
          generic map (    
            width    => 2,
            AsynReset=> false)
          port map (
              reset  => jc1_reset, -- synchronous reset
              clk    => clk_50KHz,
              en     => vcc,
              q      => jc1_q);


  -------------------------------------------------------------------
  -- Johnson Counter 2 
  -- (1) Use this counter to generate 20 us slow clock.
  -- (2) It is also used to divide a period of time into time slots.
  --     It counts for small time slot which
  --     is 1 us wide, add up to total 20 slots. 
  -- It should be synchronized with JCount1. 
  -------------------------------------------------------------------
   jcnt2: JCounter          
          generic map (    
            width    => 10,
            AsynReset=> true) -- asynchronous reset
          port map (
            reset  => reset,  -- asynchronous reset!
            clk    => clk_1MHz,
            en     => vcc,
            q      => jc2_q);

  -------------------------------------------------------------------
  -- Bit Register
  -- It accumulates 8 bits of data according to the strobes of
  -- bitreg_en, and output a byte of data.
  -------------------------------------------------------------------
  bitreg_i: BitReg
      generic map ( numBits => 8)
      port map (
            clk   => clk_1MHz,    -- for each bit, use faster clock
            reset => reset,       -- asynchronous reset !
            din   => din,         -- one bit
            en    => bitreg_en,   -- std_logic_vector(7 downto 0)
            dout  => data_i);     -- a byte
            
    
   -- This is the enable signal for the BitReg. When a bit of data
   -- is ready, the BitReg is enabled to load this bit of data
   -- at corresponding bit. For example: bitreg_en = "00001000"
   -- means the data bit will be stored into the register bit 3.
   -- This enable strobe is asserted only one clock period of 1 us.
   -- It's generated from the output of SR1, which is used to
   -- count for 8 bits in a byte of data. It is also controlled by
   -- the numberbits_valid, which indicates a valid data bit received
   -- from the Serial Number Device.
   bitreg_en <= sr1_q when (databit_valid='1') else (others=>'0'); 
   

  -------------------------------------------------------------------
  -- Byte Register
  -- It accumulates 6 bytes of data (serial number) according to
  -- the strobes of bytereg_en, and output the serial number.
  -------------------------------------------------------------------
  
    bytereg_i: ByteReg
      generic map ( numBytes => 6)
      port map (
            clk   => clk_50KHz,   -- for each byte, can use slower clock
            reset => reset,       -- asynchronous reset !
            din   => data_i,      -- one bit
            en    => bytereg_en,  -- std_logic_vector(5 downto 0)
            dout  => sn_data);    -- 48 bits parallel output
            
    -- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% MODIFICA %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	 -- modificato in modo da memorizzare i primi 6 byte ricevuti
	 
     bytereg_en <= sr2_q(5 downto 0) when (thisState = RX_DATA) else (others=>'0');
                                  -- only enables for the 48 bits
                                  -- serial number by bypassing
                                  -- the first byte (family code)
                                  -- and the last byte (crc code)
   
	-- %%%%%%%%%%%%%%%%%%%%%%%%%%%%%% FINE MODIFICA %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
	
   ------------------------------------------------------------------------
   -- Check CRC and Generate CRCOK signal
   -- Use CRCReg to calculate CRC value
   -- Latch crcok result when reach the last state (IDLE state)
   --
   -- Note: Use generic to turn on or off this CRC check circuit.
   -- If CheckCRC is false, this circuit will be removed to save
   -- register resources. And CRCOK output will be asserted high as
   -- long as all the data are received. So it won't reflect the CRC
   -- checking result.