generale_map.mrp

simple thermometr in vhdl

Release 9.2i Map J.36
Xilinx Mapping Report File for Design 'generale'

Design Information
------------------
Command Line   : C:\Xilinx92i\bin\nt\map.exe -ise C:/Documents and
Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA/VGAterm/VGAterm.ise
-intstyle ise -p xc2s50-tq144-5 -cm area -pr b -k 4 -c 100 -tx off -o
generale_map.ncd generale.ngd generale.pcf 
Target Device  : xc2s50
Target Package : tq144
Target Speed   : -5
Mapper Version : spartan2 -- $Revision: 1.36 $
Mapped Date    : Sun Dec 02 20:42:29 2007

Design Summary
--------------
Number of errors:      0
Number of warnings:    3
Logic Utilization:
  Total Number Slice Registers:     491 out of  1,536   31%
    Number used as Flip Flops:                    474
    Number used as Latches:                        17
  Number of 4 input LUTs:         1,235 out of  1,536   80%
Logic Distribution:
    Number of occupied Slices:                         753 out of    768   98%
    Number of Slices containing only related logic:    753 out of    753  100%
    Number of Slices containing unrelated logic:         0 out of    753    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:        1,293 out of  1,536   84%
      Number used as logic:                     1,235
      Number used as a route-thru:                 56
      Number used as Shift registers:               2
   Number of bonded IOBs:             9 out of     92    9%
      IOB Flip Flops:                               3
   Number of GCLKs:                   3 out of      4   75%
   Number of GCLKIOBs:                1 out of      4   25%

   Number of RPM macros:            1
Total equivalent gate count for design:  12,686
Additional JTAG gate count for IOBs:  480
Peak Memory Usage:  132 MB
Total REAL time to MAP completion:  6 secs 
Total CPU time to MAP completion:   4 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network XLXI_15/N0 has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 1
   more times for the following (max. 5 shown):
   XLXI_15/N1
   To see the details of these warning messages, please use the -detail switch.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   XLXI_24/XLXI_4/ow_master_i/conv_ok_or0000 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) removed
   4 block(s) optimized away
   2 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "XLXI_15/N0" is sourceless and has been removed.
The signal "XLXI_15/N1" is sourceless and has been removed.
Unused block "XLXI_15/XST_GND" (ZERO) removed.
Unused block "XLXI_15/XST_VCC" (ONE) removed.

Optimized Block(s):
TYPE 		BLOCK
VCC 		XLXI_16
GND 		XLXI_24/XLXI_5

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clk88                              | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       |
| hs                                 | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
| onewire                            | IOB     | BIDIR     | LVTTL       | 12       | SLOW | INFF     | PULLUP   | IFD   |
| rgb<0>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rgb<1>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rgb<2>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rgb<3>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rgb<4>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| rgb<5>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| vs                                 | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------
XLXI_15_0                               

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.

----------------------

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
No timing report for this architecture.

Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings

Section 13 - Control Set Information
------------------------------------
No control set information for this architecture.