generale.drc

simple thermometr in vhdl

WARNING:PhysDesignRules:372 - Gated clock. Clock net
   XLXI_24/XLXI_4/ow_master_i/conv_ok_or0000 is sourced by a combinatorial pin.
   This is not good design practice. Use the CE pin to control the loading of
   data into the flip-flop.
DRC detected 0 errors and 1 warnings.